This paper presents new results on miniaturized pentacene thin film transistors (TFTs) fabricated on a spin coated polyimide (PI) film. Patterning steps, which are vital for the integrity and electrical performance of organic TFTs, were done using resistless shadow-mask lithography with two high precision MEMS fabricated stencils, thus avoiding solvents and high temperature processes. Both pentacene and source-drain (S/D) electrodes were directly patterned through stencils with high accuracy on wafer scale. The TFTs have been characterized before and after peeling the flexible PI film off the rigid surface, showing full transistor functionality in both cases.
a b s t r a c tIn this work double-gate pentacene TFT architecture is proposed and experimentally investigated. The devices are fabricated on a polyimide substrate based on a process that combines three levels of stencil lithography with standard photolithography. Similarly to the operation of a conventional double-gate silicon FET, the top-gate bias modulates the threshold voltage of the bottom-gate transistor and significantly improves the transistor sub-threshold swing and leakage current. Moreover, the double gate TFT shows good promise for the enhancement of I ON /I OFF , especially by the control of I OFF in devices with poor top interfaces.
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