Double-gate pentacene thin-film transistor with improved control in sub-threshold region

Tsamados, Dimitrios; Cvetkovic, Nenad V.; Sidler, Katrin; Bhandari, Jyotshna; Savu, Veronica; Brugger, Juergen; Ionescu, Adrian M.

doi:10.1016/j.sse.2010.04.019

Cited by 17 publications

(17 citation statements)

References 14 publications

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“…Through these, material for the transistor gates is deposited. The stencil is manually aligned to the substrate with 2 lm [9] accuracy using a customized SUSS MA/BA 6 mask aligner [10]. The clamped substrate-stencil setup is placed in an evaporator where 100 nm thick Al gates are deposited.…”

Section: Contents Lists Available At Sciencedirectmentioning

confidence: 99%

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Sacchetto

Savu

Micheli

et al. 2011

Microelectronic Engineering

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a b s t r a c tWe report on a fully CMOS compatible fabrication method for ambipolar silicon nanowire FinFETs. The low thermal budget processing, compatible with monolithic 3D device integration, makes use of low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si) and SiO 2 layers as well as metal gate patterning using stencil lithography, demonstrated for the first time. FinFETs with stenciled Al gates are successfully co-fabricated with polycrystalline silicon X-gated devices. Stencil lithography is envisaged as a key enabler for gate patterning on 3D structures, such as vertically stacked nanowire transistors.

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Section: Contents Lists Available At Sciencedirectmentioning

confidence: 99%

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Sacchetto

Savu

Micheli

et al. 2011

Microelectronic Engineering

Self Cite

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“…Besides, for the transistors with intrinsic pentacene channel, the mobility is averaged to be 0.09 cm 2 V À1 s À1 , which is among the highest mobility values reported for top-gate pentacene-based organic transistors. 7,13,14 For the depletion transistors with p-doped pentacene channel, the average mobility is 0.05 cm 2 V À1 s À1 , whereas for the inversion transistors with n-doped pentacene channel, the mobility is 0.03 cm 2 V À1 s À1 . The comparatively small mobility of doped-channel transistors is related to the structural phase transition of the pentacene film from crystalline to amorphous at increased doping concentration.…”

Section: Top-gate Organic Depletion and Inversion Transistors With Domentioning

confidence: 99%

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Liu

Kasemann

Leo

2015

Applied Physics Letters

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Organic field-effect transistors constitute a vibrant research field and open application perspectives in flexible electronics. For a commercial breakthrough, however, significant performance improvements are still needed, e.g., stable and high charge carrier mobility and on-off ratio, tunable threshold voltage, as well as integrability criteria such as n- and p-channel operation and top-gate architecture. Here, we show pentacene-based top-gate organic transistors operated in depletion and inversion regimes, realized by doping source and drain contacts as well as a thin layer of the transistor channel. By varying the doping concentration and the thickness of the doped channel, we control the position of the threshold voltage without degrading on-off ratio or mobility. Capacitance-voltage measurements show that an inversion channel can indeed be formed, e.g., an n-doped channel can be inverted to a p-type inversion channel with highly p-doped contacts. The Cytop polymer dielectric minimizes hysteresis, and the transistors can be biased for prolonged cycles without a shift of threshold voltage, indicating excellent operation stability.

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“…Through these, material for the transistor gates is deposited. The stencil is manually aligned to the substrate with 2-m [42] accuracy using a customized SUSS MA/BA6 mask aligner [43]. The clamped substrate-stencil setup is placed in an evaporator where 100-nm-thick Al gates are deposited.…”

Section: Low-temperature Fabrication Of -Si Nanowires Fetsmentioning

confidence: 99%

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

2012

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| Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/ semiconductor surface. The combination of these two memristive effects into multiterminal metal-oxide-semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal-oxide-semiconductor (CMOS) cofabrication with a CMOS-compatible process.

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Double-gate pentacene thin-film transistor with improved control in sub-threshold region

Cited by 17 publications

References 14 publications

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Ambipolar silicon nanowire FETs with stenciled-deposited metal gate

Top-gate organic depletion and inversion transistors with doped channel and injection contact

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

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