Modified Oxygen Vacancy Induced Fermi Level Pinning Model Extendable to P-Metal Pinning

Abstract

Typical p-metals show similar effective work functions close to p+ polycrystalline silicon (poly-Si) pinning position irrespective of materials after high-temperature process. We found that this phenomenon can be explained by the modified Vo model taking into account the effect of Si substrate. Oxygen absorption by Si substrate and subsequent electron transfer to metal electrode clearly explain the p-metal Fermi level pinning as well as p+ poly-Si pinning. In addition, unsuppressed Fermi level pinning by insertion of barrier layer at p+ poly-Si/barrier layer/high-k gate stack, which is one of the open issues concerning p+ poly-Si pinning, has the same overall reaction scheme. The modified model also consistently explains this phenomenon.

Improving the electrical characteristics of MOS transistors with CeO2/La2O3 stacked gate dielectric

“…It was suggested that the threshold voltage control has become one of the major concerns for the actual application of high-k gate dielectrics in CMOS devices [14][15][16][17][18]. The difficulty in threshold voltage control is due to the high fixed charge density in the high-k dielectric and the Fermi level pinning effect at the high-k/ metal interface [14].…”

“…Another proposal for the Fermi level pinning is related to the oxygen diffusion into the Si channel. This leaves behind a oxygen vacancy in the dielectric and two electrons fall in the gate Fermi level [18]. However, based on a series of experiments on HfLaO x dielectric films, Yamamoto et al suggested that the flatband shift should not be due to the Fermi level pinning at the HfLaO x /metal interface [19].…”

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

“…The total energy gaining of the V o generation reaction by the partial oxidation of poly-silicon followed by the electron transfer from HfO 2 to poly-silicon, DG total , is given by the following reaction equation [246]:…”

“…Due to the modification of work functions and equivalent oxide thickness, any reaction at gate/dielectric interface can be of major concerns. Another drawback to successful implementation of metal gate electrodes with the proper controlled work functions is also Fermi level pinning effects [246,259], which will push the gate effective work function to mid-gap position. The problems for pFET gates and simple metals such as Re, Ru or Ir arise because these metals are permeable to oxygen and hydrogen.…”

Systematic study on work-function-shift in metal/Hf-based high-k gate stacks

“…In addition, Akasaka et al constructed a modified V O model to understand process-dependent p-metal FLP by taking into account V O formation due to oxygen transport through the SiO 2 interlayer to the Si substrate. 7 In contrast, for the latter case, the increase in WF for inert metal electrodes on Hf-based oxides can be explained by interface hybridization between the large occupied state of metal electrodes and the unoccupied Hf 5d state of the Hf-based oxides. This interface hybridization causes charge transfer in the opposite direction for the V O formation, that is, the generalized charge neutrality level ͑ G CNL ͒ model.…”