Improving the electrical characteristics of MOS transistors with CeO2/La2O3 stacked gate dielectric

Yang, Bong-Jun; Wong, Hei; Kakushima, Kuniyuki

doi:10.1016/j.microrel.2011.10.009

Cited by 19 publications

(6 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In addition, a strong Si‐N bonding as well as relaxation of strained bonds between the CeO 2 passivation layer and Si surface could be realized through the utilization of nitrogen ambient that led to a reduction in interface trap density 36 . Similar findings have been revealed for HfO 2 37 as well as stacking CeO 2 /La 2 O 3 38 passivation layer subjected to nitridation, wherein an enhancement in carrier mobility as well as stable threshold voltage were established for the fabricated devices. Besides these beneficial effects of nitrogen ambient, the inbound of nitrogen species during annealing might contribute to the displacement of oxygen from the CeO 2 lattice, and hence encouraging the formation of oxygen vacancies unfavorable for passivation layer 39,40 …”

Section: Introductionsupporting

confidence: 65%

Effects of post‐deposition annealing of cerium oxide passivation layer in nitrogen‐oxygen‐nitrogen ambient

Shekkeer

Cheong

Quah

2022

Intl J of Energy Research

View full text Add to dashboard Cite

Summary Effects of post‐deposition annealing temperature (400°C, 600°C, 800°C and 1000°C) onto metal‐organic decomposed cerium oxide (CeO2) precursor spin‐coated on n‐type Si substrate was carried out in nitrogen‐oxygen‐nitrogen ambient. The capability of nitrogen to inhibit further oxidation of the Si surface by attaching to the oxygen vacancies sites was reported. Excessive formation of SiO2 interfacial layer however occurred at 1000°C, surpassing the thickness of the CeO2 passivation layer, leaving behind nitrogen dangling bonds that were inefficient in restricting further oxidation of the Si surface, and hence a permanent dielectric breakdown happened at an electric field of 0.98 MV/cm. The CeO2 passivation layer annealed at 800°C broke down at 4.85 MV/cm and possessed relatively low Dit, Qeff, and slow trap density with negligible formation of interfacial layer, which promoted its use as a promising high k passivation layer.

show abstract

Section: Introductionsupporting

confidence: 65%

Effects of post‐deposition annealing of cerium oxide passivation layer in nitrogen‐oxygen‐nitrogen ambient

Shekkeer

Cheong

Quah

2022

Intl J of Energy Research

View full text Add to dashboard Cite

show abstract

“…HfAlO offers interesting performance from this perspective with respect to SiO2 or Si3N4, consistently to the band-gap and the high-k value reported, [1][2][3]. Although further materials (such as Ta2O5 or La2O3/CeO2) demonstrate a higher capacitance density [4][5][6][7], HfAlO takes advantage of the low leakage current density for the higher band offset [1][2][3], [8]. This latter is crucial at the high temperature reached in operating condition.…”

Section: Introductionmentioning

confidence: 52%

Transmission line pulse (TLP) as integrative method for the investigation of ultra-fast trapping mechanisms on high-k MIM

Merlo

Rossetto

Cerati

et al. 2019

Microelectronics Reliability

View full text Add to dashboard Cite

This paper discusses the transmission line pulse (TLP) analysis, generally used for electrostatic discharge (ESD) device characterization, as high potential usable tool also for non-ESD structures.TLP technique, combined with DC and pulsed I-V characterization, is performed to study the contribution of trap states on current conduction in metal-insulator-metal (MIM) capacitors with an HfAlO stack. The importance of the above mentioned methods is demonstrated by comparing two generations of samples with slightly different charge trapping mechanisms; their impact on the current conduction is furthermore studied by decreasing the pulse width down to 50nsec.TLP analysis is finally discussed as interesting method to investigate the influence of trap states on the device robustness. The evaluation of breakdown voltage for different time pulses allows to discriminate whether different failure mechanisms occur or not and to establish the impact of trap states on short-term reliability.

show abstract

“…This postprocessing step at comparatively low temperatures of 500 C, which is compatible with a gate-last process, 18 enables the growth of highly ordered, C-type La 2 O 3 (111) films with a low defect concentration, which was shown to result in reduced Coulomb scattering by reducing the fixed oxide charge, reduced leakage currents, and a higher channel mobility, 18,19 suggesting that also the modest interface postoxidation helps in improving the electrical properties of the gate stack. Together with the prepassivation approach, these findings may pave the road toward the realization of rare-earth based, epitaxial, highly crystalline high-k oxides on silicon.…”

Section: Discussionmentioning

confidence: 99%

“…14 Very recently, a strong improvement in electrical properties was observed when a thin cerium oxide was deposited on top, which was explained in a scenario where, driven by the difference in oxygen chemical potential in lanthana and ceria, oxygen vacancies at the interface and in the LaO x film were speculated to be healed by additional oxygen ions provided by the ceria adlayer. [17][18][19] Earlier, we have reported the beneficial use of an atomic layer of chlorine for substrate passivation, enabling the growth of well-ordered Ce 2 O 3 (111) (Refs. 20 and 21) and Pr 2 O 3 (111) (Ref.…”

Section: Introductionmentioning

confidence: 99%

Epitaxial, well-ordered ceria/lanthana high-k gate dielectrics on silicon

Flege

Kaemena

Schmidt

et al. 2014

Journal of Vacuum Science &Amp; Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phen

View full text Add to dashboard Cite

It is shown that the growth of epitaxial lanthana films on silicon may be achieved by substrate prepassivation using an atomic layer of chlorine, which prevents silicon oxide and silicate formation at the oxide–silicon interface. Postdeposition of two layers of cerium oxide facilitates the healing of structural defects within the La2O3 film, strongly increasing its crystallinity at the expense of a slightly more oxidized interfacial layer below. Together, the approach of combining Cl prepassivation and the ceria overgrowth results in an epitaxial, high-quality ceria/lanthana gate stack suitable for high-k integration in a gate-last process.

show abstract

Improving the electrical characteristics of MOS transistors with CeO2/La2O3 stacked gate dielectric

Cited by 19 publications

References 18 publications

Effects of post‐deposition annealing of cerium oxide passivation layer in nitrogen‐oxygen‐nitrogen ambient

Effects of post‐deposition annealing of cerium oxide passivation layer in nitrogen‐oxygen‐nitrogen ambient

Transmission line pulse (TLP) as integrative method for the investigation of ultra-fast trapping mechanisms on high-k MIM

Epitaxial, well-ordered ceria/lanthana high-k gate dielectrics on silicon

Contact Info

Product

Resources

About