Modelling of 1T-NOR flash operations for consumption optimization and reliability investigation

Coignus, J.; Torrente, Giulio; Vernhet, Alexandre; Renard, S.; Roy, D.; Reimbold, G.

doi:10.1109/irps.2016.7574630

Cited by 3 publications

(2 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The superposition of Is(tP) for both devices is the evidence of a good floating gate potential extraction. The source current that flows in the memory transistor channel depends on the floating gate potential [6,17]. It indicates the programming efficiency loss and the charge trapping localization [20].…”

Section: Adaptive Cycling On Dummy Cellmentioning

confidence: 99%

“…In the semiconductor non-volatile memories world, we observe an increasing production of resistive switching devices [1][2][3][4], even if the floating gate Flash still share a large percentage of the market. The charge storage devices, for embedded applications, are today scaled toward the 40nm node and beyond [5][6][7]. The Flash programming scheme has been adapted to satisfy the new constraints imposed by the smart connected object application field, to remain competitive with respect to the new devices, very aggressive in terms of energy consumption and scaling [8,9].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction

Marca

Postel-Pellerin

Kempf

et al. 2018

Microelectronics Reliability

View full text Add to dashboard Cite

Nowadays, the study of physical mechanisms that occur during Flash memory cell life is mandatory when reaching the 40nm and beyond nodes in terms of reliability. In this paper we carry out a complete experimental method to extract the floating gate potential evolution during the cell aging. The dynamic current consumption during a Channel Hot Electron operation for a NOR Flash is a proper quantitative marker of the cell degradation. Here both drain and bulk currents are measured and monitored throughout the endurance tests. We coupled these characteristics with quasi-static measurements to correlate the cell degradation with an equivalent transistor. The final goal is to be able to split the physical effects of repetitive hot carrier and Fowler-Nordheim operations, typical of Flash memories, to extract the electrical parameters evolution on a simple equivalent transistor.

show abstract

Section: Adaptive Cycling On Dummy Cellmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction

Marca

Postel-Pellerin

Kempf

et al. 2018

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

Microscopic Analysis of Erase-Induced Degradation in 40 nm NOR Flash Technology

Torrente

Coignus

Vernhet

et al. 2016

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Gul,

Shams,

Al-Khalili

2023

Micromachines

View full text Add to dashboard Cite

Artificial intelligence (AI) has revolutionized present-day life through automation and independent decision-making capabilities. For AI hardware implementations, the 6T-SRAM cell is a suitable candidate due to its performance edge over its counterparts. However, modern AI hardware such as neural networks (NNs) access off-chip data quite often, degrading the overall system performance. Compute-in-memory (CIM) reduces off-chip data access transactions. One CIM approach is based on the mixed-signal domain, but it suffers from limited bit precision and signal margin issues. An alternate emerging approach uses the all-digital signal domain that provides better signal margins and bit precision; however, it will be at the expense of hardware overhead. We have analyzed digital signal domain CIM silicon-verified 6T-SRAM CIM solutions, after classifying them as SRAM-based accelerators, i.e., near-memory computing (NMC), and custom SRAM-based CIM, i.e., in-memory-computing (IMC). We have focused on multiply and accumulate (MAC) as the most frequent operation in convolution neural networks (CNNs) and compared state-of-the-art implementations. Neural networks with low weight precision, i.e., <12b, show lower accuracy but higher power efficiency. An input precision of 8b achieves implementation requirements. The maximum performance reported is 7.49 TOPS at 330 MHz, while custom SRAM-based performance has shown a maximum of 5.6 GOPS at 100 MHz. The second part of this article analyzes the FinFET 6T-SRAM as one of the critical components in determining overall performance of an AI computing system. We have investigated the FinFET 6T-SRAM cell performance and limitations as dictated by the FinFET technology-specific parameters, such as sizing, threshold voltage (Vth), supply voltage (VDD), and process and environmental variations. The HD FinFET 6T-SRAM cell shows 32% lower read access time and 1.09 times better leakage power as compared with the HC cell configuration. The minimum achievable supply voltage is 600 mV without utilization of any read- or write-assist scheme for all cell configurations, while temperature variations show noise margin deviation of up to 22% of the nominal values.

show abstract

Modelling of 1T-NOR flash operations for consumption optimization and reliability investigation

Cited by 3 publications

References 8 publications

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction

Quantitative correlation between Flash and equivalent transistor for endurance electrical parameters extraction

Microscopic Analysis of Erase-Induced Degradation in 40 nm NOR Flash Technology

FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis

Contact Info

Product

Resources

About