IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004.
DOI: 10.1109/iedm.2004.1419113
|View full text |Cite
|
Sign up to set email alerts
|

Mobility improvement for 45nm node by combination of optimized stress control and channel orientation design

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
4
1

Citation Types

0
16
1

Publication Types

Select...
5
2
1

Relationship

0
8

Authors

Journals

citations
Cited by 29 publications
(17 citation statements)
references
References 0 publications
0
16
1
Order By: Relevance
“…From a classical Hall effect approach, this is a pretty small angular deflection to cause such a noticeable Ms-B behavior. Theoretical, modeling and simulation research work in progress at ]NAOE [8], shows that the 45° rotation of the channel axis with respect to the wafer notch, and the use of strain engineering [9] results in a channel in-plane non-homogeneous strain (see Fig. 2) [10].…”
Section: Experimental Findings Analysis Modeling and Simulationsmentioning
confidence: 99%
“…From a classical Hall effect approach, this is a pretty small angular deflection to cause such a noticeable Ms-B behavior. Theoretical, modeling and simulation research work in progress at ]NAOE [8], shows that the 45° rotation of the channel axis with respect to the wafer notch, and the use of strain engineering [9] results in a channel in-plane non-homogeneous strain (see Fig. 2) [10].…”
Section: Experimental Findings Analysis Modeling and Simulationsmentioning
confidence: 99%
“…However, it requires an extra mask to selectively remove the SMT tensile layer on the PMOS region since the tensilestress liner degrades the hole mobility in PMOS. In low-power technology, the 45d rotated wafer ( 100 orientation on the (100) substrate) has been chosen considering both performance and cost for the following reasons: 1) Intrinsic hole mobility is higher compared to that of a normal wafer, and 2) hole mobility is insensitive to stress, hence the tensile-stress liner can be directly applied on the whole wafer to improve NMOS perfor- mance without degrading PMOS performance, thus reducing the cost [2], [3]. The blanket-SMT process is expected to be implemented on the 45d rotated wafer without degrading PMOS performance.…”
Section: Introductionmentioning
confidence: 99%
“…MOSFETs performance depends also on the substrate orientation. It was already demonstrated that 45°-rotated substrates can improve pMOS device performance without degrading the nMOS one [6]. However, the best channel orientation depends on the stress techniques and levels.…”
Section: Introductionmentioning
confidence: 99%