Meeting the Electrical, Optical, and Thermal Design Challenges of Photonic-Packaging

Abstract

Integrated photonics is a promising route toward high-performance next-generation ICT and sensing devices. Although fiber-packaging is perhaps the most widely discussed obstacle to low-cost photonic devices, electronic-photonic integration and thermal-stabilization are also significant design considerations that need to be properly managed. Using a state-of-the-art Si-photonic optical-network-unit as a worked example, we illustrate some key challenges and solutions in the field of photonicpackaging. Specifically, we describe a novel solder-reflow bonding process for the face-to-face three-dimensional (3-D) integration of photonic and electronic integrated circuits, discuss current and future multichannel fiber-alignment techniques, and investigate the coefficient-of-performance of the thermo-electric cooler that stabilizes the temperature of the photonic components. The challenge of photonic-packaging is to simultaneously satisfy these electrical, optical, and thermal design requirements on small-footprint devices, while establishing a route to scalable commercial implementation.

In situ 3D nanoprinting of free-form coupling elements for hybrid photonic integration

“…The same applies to adiabatic mode converters 21 , which rely on continuous transformation of mode profiles by evanescent coupling to tapered silicon photonic waveguides. Surface coupling can considerably relax the alignment tolerances to values 17 of  2.5 µm, but still requires active alignment 3 . In addition, grating couplers are inherently wavelength-dependent with typical bandwidths of less than 30 nm, and the resulting assemblies often lead to unfavorable arrangements with fibers mounted typically perpendicularly to the chip surface.…”

Photonic Wire Bonding and 3D Nanoprinting in Photonic Integration – from Lab Demonstrations to Production

“…Single-mode chip-to-chip and fiber-to-chip interfaces represent a key challenge in packaging and assembly of photonic integrated systems [1]. On the optical side, this challenge comprises two main aspects: First, on-chip waveguides frequently feature small mode-field diameters, in particular when high index-contrast silicon-photonic (SiP) or InP-based components are involved.…”

Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

“…The 10 × 10 µm footprint of the grating-coupler is chosen to match the 8-10 µm MFD of a standard telecom fiber, and consists of a (periodic) array of ≈20 trenches partially-etched into the 220 nm Si-layer [12]. A simple relation exists between the peak wavelength of the coupler (λ), the pitch of the trenches (P), the effective index of the grating-coupler region (n e ), the index of the oxide-layer (n o ), and the angle-of-incidence (θ) of the fiber-mode: λ = P (n e -n o sin θ), where the value of n e is determined by the etch-depth and duty-cycle of the trenches, as well as the polarization of the fiber-mode.…”

“…'Photonic Packaging' is the catch-all term used to describe the range of techniques and technical competencies needed to make the optical, electrical, thermal, mechanical (and sometimes chemical) connections between a PIC and the outside world [9][10][11][12]. While Fiber-to-PIC coupling is perhaps the best-known aspect of photonic packaging, the field also includes the integration of laser-chips, microoptics, electronic-chips, and micro-fluidics on PICs; the high-speed (25 Gbps) routing and impedancematching of transmission-lines from external connectors to the microscopic photonic components on the PIC; and the efficient thermal cooling and thermal-stabilization needed to keep the PIC within its operational range-see Figures 1 and 2.…”

“…This is especially the case in more advanced photonic devices, where there is the simultaneous need for several different varieties of packaging, i.e., multichannel Fiber-to-PIC coupling, a vertically integrated driver-chip, and a high-speed connection, and a thermo-electric cooler [12]. To ensure that these devices are fully-functional when fabricated and assembled requires the adoption of packaging design rules (PDRs) up front, at the Si-PIC design stage.…”