Layout-dependent STI stress analysis and stress-aware RF/analog circuit design optimization

Abstract

With the continuous shrinking of feature size, various effects due to shallow-trench-isolation (STI) stress are becoming more and more significant. The resulting nonuniform distribution of stress affects the MOSFET characteristics and hence changes the circuit behavior. This paper proposes a complete flow to characterize the influence of STI stress on performance of RF/analog circuits based on layout design and process information. An accurate and efficient FEM-based stress simulator has been developed to handle the layout dependence. A comprehensive MOSFET model is also proposed to capture the effects of STI stress on mobility, threshold voltage, and leakage current. The influence of layout-dependent STI stress on the circuit performance is further studied, and the corresponding optimization strategies to circuit design are discussed. A realistic PLL design realized using 90nm CMOS technology is used as a test case for the proposed approach. . IntroductionAs CMOS technology is moving to sub-90nm nodes, the mechanical stress, which is used to be the secondary concern of the circuit design, now becomes one of the major factors determining circuit performance. Different from other intentional mechanical stresses, STI stress, which is exerted by STI wells on active region of the device, is inevitably formed and has increasingly significant impact on device behavior, especially in aggressively scaled-down CMOS technology.A few papers [1][2][3][4][5] have reported the influence of STI stress on device characteristics. In [6-8], some empirical models have been proposed, which mainly focus on relatively simple cases. Moreover, these studies are all conducted at device level, and thus do not consider the effects on MOSFET characteristics due to complex STI stress distribution on a real die. It is desirable to develop an accurate and efficient method to analyze the influence of the STI stress on device/circuit performance comprehensively at a full-chip level.Mobility change, which is responsible for the driving current and many other device behaviors, is one of the most important factors induced by STI stress. The most widely used Berkeley Short-channel IGFET Model (BSIM) SPICE model (revision 4.6 and higher) does not fully consider the influence of two-dimensional (2-D) STI stress. Recently, Kahng proposed a model that relates the transistor mobility to stress induced by the width of STI regions [9-10]. However, this model focuses only on simplistic situations, so it cannot be applied to complex layout analysis.Leakage current grows significantly with the ever-shrunk gate length, and it is also affected significantly by STI stress. In [11][12], the effects of the STI stress on leakage current at 130nm and 65nm nodes have been discussed. However, to our knowledge, quantitative analysis and models on these effects are not available.Besides, the circuit performance will change under the influence of STI stress. The delay of digital circuits under the influence of the width change of STI is studied in [10] and [13]. However,...

Design procedure for multifinger MOSFET two‐stage OTA with shallow trench isolation effect

“…The various layout aware design methodologies were proposed to analyse MOS characteristics and the circuit performance under LDEs [5][6][7][8][21][22][23][24]. An accurate and efficient finite-element method-based stress simulator has been developed to characterise the influence of STI stress on the performance of RF and analogue circuits by considering detailed layout and process information [5].…”

“…In the designs proposed in [5][6][7][8][21][22][23][24], the number of fingers was varied on a trial and error basis until the design specifications are met. Apparently, redesigning the circuit and redrawing the layout at each iteration is the major drawback of these procedures.…”

“…In addition, as the MOSFET sizes reach the nanoscale regime, a new type of variability was induced known as layout‐dependent effects (LDEs) [2–24], which becomes a critical issue in modern analogue and mixed‐signal circuit designs and is used to be the secondary concern of the circuit design. In particular, two dominant LDEs such as shallow trench isolation (STI) [8–19] and well proximity effect (WPE) [4, 20] are found to significantly affect the threshold voltage and mobility of devices in advanced technology nodes. This is true even in the general analogue integrated circuit building blocks.…”

“…Where, the LDEs were transformed into a non‐linear analytical placement models. In order to verify the effect of STI stress, a ring oscillator has been designed by varying the number of fingers of the device [8]. As changes, there is a deviation in frequency performance of low noise amplifier (LNA) and oscillator.…”

“…As changes, there is a deviation in frequency performance of low noise amplifier (LNA) and oscillator. In [8], the oscillation frequency is adjusted near to original value by tweaking the of PMOS and NMOS devices. The performance of LNA is analysed as a function of with fixed width transistor [21].…”