Abstract-This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasiticaware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.
In this paper we present the language Stratus dedicated to the parametrized generation of VLSI modules. Stratus extends the Python language with a set of methods and functions for the procedural generation of netlist and layout views of structured cell based designs. It also provides a programming framework for the development of various optimization techniques that can be applied during module generation. From the designer's point of view, Stratus takes full advantage of Python: a portable, interpretative, easy to learn and objectoriented language. Stratus is the design capture component of the open-source academic Physical Synthesis platform Coriolis, based upon the Hurricane C++ integrated data-base, which provides both C++ and Python high level APIs. Stratus extends this Python API, and allows the designer to use both low level and high level placement, global routing and detailed routing directives.
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