Abstract-This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasiticaware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.

International audienceThis chapter presents a designer-assisted analog synthesis flow that is fully controlled by the designer and offers an intuitive design approach. The designer knowledge to conceive an analog IP is the key element of the synthesis flow, it is taken into account to automatically generate the analog IP design procedure and the physical view. Thus both consistency and accuracy of the final design are ensured. The presented flow bridges the gap between the two traditional approaches related to analog synthesis, namely the simulation-based and the knowledge-based approaches. It combines accuracy from simulation-based approaches with speed of computation from knowledge-based approaches. The proposed analog synthesis flow is composed of an accurate hierarchical sizing and biasing tool and a parameterizable layout generation tool. To demonstrate the effectiveness of the proposed flow, a fully differential transconductor was completely synthesized in 130nm CMOS technology to respect some performance specifications set by the designer. The obtained very low runtime is due to the introduction of design knowledge during both sizing and layout generation

In this paper, a new method for developing smart parameterized generators for analogue devices is presented. A device is an atomic analogue cell that performs an elementary and standard function such as the differential pair and the current mirror. A device is smart since it can be electrically and physically adapted. In the proposed method, the device sizes and biases are first computed using dedicated sizing operators based on the MOS transistor model and the foundry Design Kit. Once transistor sizes are computed, they are fed to a layout generation tool which offers different layout styles for the same device. The layout is generated with the layout dependent parasitics, including stress effects. These parasitics are then taken into account by the sizing operators. Therefore a loop between sizing and layout generation can be set and executed until the device specifications are met. The method is applied to a differential pair with several layout styles and two distinct technologies.

This paper studies the matching and the stress effect problems that appear in deep submicron CMOS technologies. These effects significantly affect the electrical behavior of CMOS transistors. We propose a method to compute stress effect parameters resulting from different layout styles such as interdigitated and symmetrical styles. We apply this method to a transistor device and a differential pair device. We also quantify the errors due to transistor folding and stress effects in 65nm CMOS technology for different device layouts. The results show the effectiveness of the proposed method.