2012
DOI: 10.1016/j.vlsi.2011.05.004
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Towards accelerating irregular EDA applications with GPUs

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Cited by 7 publications
(2 citation statements)
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“…A final NR Algorithm 1 is composed of the following 4 steps repeated in the NR loop until a convergence is reached. The solutions of ( 5), ( 6), (7) and the result of the matrix multiplications indicated in (4) are obtained with the help of the sparse matrix techniques. Moreover, a two-level bypassing process may be easily implemented: bypassing of nonlinear elements in step 1 of Algorithm 1 during the calculation of stamps for nonlinear elements and bypassing of blocks in step 4 during the calculation of their stamps indicated in (4).…”
Section: The Parallelizable Bbd-based Algorithmmentioning
confidence: 99%
“…A final NR Algorithm 1 is composed of the following 4 steps repeated in the NR loop until a convergence is reached. The solutions of ( 5), ( 6), (7) and the result of the matrix multiplications indicated in (4) are obtained with the help of the sparse matrix techniques. Moreover, a two-level bypassing process may be easily implemented: bypassing of nonlinear elements in step 1 of Algorithm 1 during the calculation of stamps for nonlinear elements and bypassing of blocks in step 4 during the calculation of their stamps indicated in (4).…”
Section: The Parallelizable Bbd-based Algorithmmentioning
confidence: 99%
“…These commodity chips have enhanced their programmability to perform more general computational tasks than the graphics processing they were originally designed for. Examples include scientific computing [3] , image processing [4] , computational biology [5] , electronic design automation (EDA) [6] and data science [7] , etc. The computer video game market have driven the evolution of GPUs to yield relatively cheaper price per unit and very rapid iteration of hardware architectures.…”
Section: Introductionmentioning
confidence: 99%