Increasing the accuracy of SAT-based debugging

Sülflow, André; Fey, Görschwin; Braunstein, Cécile; Kühne, Ulrich; Drechsler, Rolf

doi:10.1109/date.2009.5090870

Cited by 21 publications

(17 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The proposed exact approach is compared to the heuristic approach of [12] and proves, that the heuristic returns high quality results. For single faults the new QBF formulation is more efficient, while the heuristic is more effective for multiple faults.…”

Section: Introductionmentioning

confidence: 94%

See 1 more Smart Citation

Using QBF to increase accuracy of SAT-based debugging

Sülflow

Fey

Drechsler

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

Abstract. The burden of debugging significantly slows down the design process of complex systems. Only limited tool support is available and a typical experience is that fixing one problem only leads to finding the next one. Here, we propose an approach that integrates formal verification with diagnosis. The approach is based on Quantified Boolean Formulas (QBF) and ensures, that counterexamples of high quality are returned. Moreover, the diagnosis algorithm only returns fault candidates that can fix all counterexamples. By this, the total number of fault candidates decreases and less iterations between verification and debugging are required.

show abstract

Section: Introductionmentioning

confidence: 94%

“…word level, no simple fault models exist. In [12] a heuristic approach was proposed to find counterexamples. That approach is limited by the power of three-valued logic simulation, i.e.…”

Section: Introductionmentioning

confidence: 99%

Using QBF to increase accuracy of SAT-based debugging

Sülflow

Fey

Drechsler

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

show abstract

“…Finding the root cause for an unsuccessful retargeting of a set of PDL commands onto some ICL network is similar to the problem of logic debugging [22]. In SAT-based logic debugging, the verified system S is expressed in Conjunctive Normal Form (CNF), denoted C S .…”

Section: Verification and Validationmentioning

confidence: 99%

Design, Verification, and Application of IEEE 1687

Zadegan

Larsson

Jutman³

et al. 2014

2014 IEEE 23rd Asian Test Symposium

View full text Add to dashboard Cite

Abstract-IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

show abstract

“…The WoLFram framework implements basic SAT-based debugging [28], [29] as well as extensions that use unsatcores to speed-up the debugging process [30] and increase the accuracy [31]. Experimental studies on SMT-based debugging show promising results [6].…”

Section: Debuggingmentioning

confidence: 99%

WoLFram- A Word Level Framework for Formal Verification

Sülflow

Kühne

Fey

et al. 2009

2009 IEEE/IFIP International Symposium on Rapid System Prototyping

View full text Add to dashboard Cite

Due to high computational costs of formal verification on pure Boolean level, proof techniques on the word level, like Satisfiability Modulo Theories (SMT), were proposed. Verification methods originally based on Boolean satisfiability (SAT) can directly benefit from this progress.In this work we present the word level framework WoLFram that enables the development of applications for formal verification of systems independent of the underlying proof technique. The framework is partitioned into an application layer, a core engine and a back-end layer. A wide range of applications is implemented, e.g. equivalence and property checking including algorithms for coverage/property analysis, debugging and robustness checking. The backend supports Boolean as well as word level techniques, like SMT and Constraint Solving (CSP). This makes WoLFram a stable backbone for the development and quick evaluation of emerging verification techniques.

show abstract

Increasing the accuracy of SAT-based debugging

Cited by 21 publications

References 11 publications

Using QBF to increase accuracy of SAT-based debugging

Using QBF to increase accuracy of SAT-based debugging

Design, Verification, and Application of IEEE 1687

WoLFram- A Word Level Framework for Formal Verification

Contact Info

Product

Resources

About