Design, Verification, and Application of IEEE 1687

Abstract

Abstract-IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

An On-Chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips

“…State-of-the-art IJTAG network models are mostly graph-based which only capture the components connectivity, (e.g. [13] and [14]). Since resolving the inter-registers structural and temporal dependencies is required for network operations, using graph-based models for modeling the network would require run-time resolution of the dependencies which can be a complex task for arbitrary networks.…”

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

“…Since both production test and in-field monitoring processes majorly depend on such embedded instruments and other features, it is of utmost importance to ensure their correct operation. Therefore, many approaches, both formal and functional, have been proposed in the literature to perform test [2]- [7], diagnosis [8] and verification [9]- [11] of IEEE 1687 networks. However, the correct operation of IJTAG-compliant infrastructure is a product of many aspects and components including the actual hardware on the chip, the respective standard descriptions, such as ICL (Instrument Connectivity Language) and PDL (Procedure Description Language) files as well as the software used to import the descriptions and control the hardware.…”

Test standards reuse for structured and cost-efficient dependability management of system-on-chips

“…Auxiliary nodes are introduced to cover special constructs such as a ScanMux followed by a branching node. A modified version of this model was introduced in [Zad14] where each ScanMux has its own graph node. Those graph models are then used for processing in a Boolean Satisfiability (SAT) solver for network verification and pattern generation.…”

“…In [Zad16a] the network is modelled in a similar fashion as in [Zad14] in order to perform a structural network decomposition into a set of scan segments, which would further optimize the execution time of the SAT-based retargeting procedure. Another directed graph model has been proposed in [Can15] where SIBs, ScanMuxs and instruments' TDRs are assigned to dedicated node types.…”

“…State-of-the-art graph-based structural models for arbitrary RSNs are being used in literature for network operations such as pattern retargeting [Bar12], [Zad14] or network test stimuli generation [Can15]. Such techniques are suitable for off-chip vector generation, such as in manufacturing tests or in debugging.…”