No abstract

No abstract

Abstract-While facing continuously shrinking feature sizes, the demand for fault tolerance in digital circuits increases. Numerous approaches to achieve robustness on the design side have been presented. But ensuring that the fault tolerance is really achieved is a tough verification problem.Here, we propose a formal model and an effective algorithm to formally prove the robustness of a digital circuit. The proposed model uses a fixed bound in time to cope with the complexity of the sequential equivalence check. The result is a lower and an upper bound on the robustness. The underlying algorithm and techniques to improve the efficiency are presented. In the experiments the method was evaluated on circuits with different fault detection mechanisms.

No abstract

After producing a chip, the functional correctness of the integrated circuit has to be checked. Otherwise, products with malfunctions would be delivered to customers, which is not acceptable for any company. During this post-production test, input stimuli are applied and the correctness of the output response is monitored. These input stimuli are called test patterns. Many algorithms for Automatic Test Pattern Generation (ATPG) have been proposed in the last 30 years. However, due to the ever increasing design complexity, new techniques have to be developed that can cope with today's circuits.Classical approaches are based on backtracking over the circuit structure. They have been continuously improved by using dedicated data structures and adding more sophisticated techniques like simplification and learning. Approaches based on Boolean Satisfiability (SAT) have been proposed since the early 1980s. Comparisons to other "classical" approaches based on FAN, PODEM and the D-algorithm have shown the robustness and effectiveness of SAT-based techniques.Recently, there is a renewed interest in SAT, and many improvements to proof engines have been proposed. SAT solvers make use of learning and implication procedures. These new proof techniques led to breakthroughs in several applications, like formal hardware verification.In this book, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation of this problem as a SAT problem is considered. Modern SAT solvers are explained and the transformation of ATPG to SAT is discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, use of various fault models and v vi PREFACE detailed experiments on multi-million gate designs. The book describes the state-of-the-art in the field, highlights research aspects and shows directions for future work.

Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported quite well using simulation or formal verification. But locating the fault site is typically a time consuming manual task. Techniques to automate debugging and diagnosis have been proposed. Approaches based on Boolean Satisfiability (SAT) have been demonstrated to be very effective.In this work debugging on the gate level is considered. Unsatisfiable cores contained in a SAT instance for debugging are used (1) to determine all suspects, and (2) to speed-up the debugging process. In comparison to standard SAT-based debugging, the experimental results show a significant speed-up for debugging multiple faults.

No abstract

Abstract