In most real world optimization problems several optimization goals have to be considered in parallel. For this reason, there has been a growing interest in Multi-Objective Optimization (MOO) in the past years. Several alternative approaches have been proposed to cope with the occurring problems, e.g. how to compare and rank the different elements. The available techniques produce very good results, but they have mainly been studied for problems of "low dimension", i.e. with less than 10 optimization objectives. In this paper we study MOO for high dimensional spaces. We first review existing techniques and discuss them in our context. The pros and cons are pointed out. A new relation called-Preferred is presented that extends existing approaches and clearly outperforms these for high dimensions. Experimental results are presented for a very complex industrial scheduling problem, i.e. a utilization planning problem for a hospital. This problem is also well known as nurse rostering, and in our application has more than 20 optimization targets. It is solved using an evolutionary approach. The new algorithms based on relation-Preferred do not only yield better results regarding quality, but also enhances the robustness significantly.

Abstract-While facing continuously shrinking feature sizes, the demand for fault tolerance in digital circuits increases. Numerous approaches to achieve robustness on the design side have been presented. But ensuring that the fault tolerance is really achieved is a tough verification problem.Here, we propose a formal model and an effective algorithm to formally prove the robustness of a digital circuit. The proposed model uses a fixed bound in time to cope with the complexity of the sequential equivalence check. The result is a lower and an upper bound on the robustness. The underlying algorithm and techniques to improve the efficiency are presented. In the experiments the method was evaluated on circuits with different fault detection mechanisms.

Abstract. The burden of debugging significantly slows down the design process of complex systems. Only limited tool support is available and a typical experience is that fixing one problem only leads to finding the next one. Here, we propose an approach that integrates formal verification with diagnosis. The approach is based on Quantified Boolean Formulas (QBF) and ensures, that counterexamples of high quality are returned. Moreover, the diagnosis algorithm only returns fault candidates that can fix all counterexamples. By this, the total number of fault candidates decreases and less iterations between verification and debugging are required.

Abstract-Equivalence checking and property checking are powerful techniques to detect error traces. Debugging these traces is a time consuming design task where automation provides help. In particular, debugging based on Boolean Satisfiability (SAT) has been shown to be quite efficient. Given some error traces, the algorithm returns fault candidates. But using random error traces cannot ensure that a fault candidate is sufficient to explain all erroneous behaviors.Our approach provides a more accurate diagnosis by iterating the generation of counterexamples and debugging. This increases the accuracy of the debugging result and yields more valuable counterexamples. As a consequence less time consuming manual iterations between verification and debugging are required -thus the debugging productivity increases.

Abstract. We present FoREnSiC, an open source environment for automatic error detection, localization and correction in C programs. The framework implements different automated debugging methods in a unified way covering the whole design flow from ESL to RTL. Currently, a scalable simulation-based back-end, a back-end based on symbolic execution, and a formal back-end exploiting functional equivalences between a C program and a hardware design are available. FoREnSiC is designed as an extensible framework. Its infrastructure, including a powerful front-end and interfaces to logic problem solvers, can be reused for implementing new program analysis or debugging methods. In addition to the infrastructure, the back-ends, and a few experimental results, we present an illustrative application scenario that shows FoREnSiC in use.

Due to high computational costs of formal verification on pure Boolean level, proof techniques on the word level, like Satisfiability Modulo Theories (SMT), were proposed. Verification methods originally based on Boolean satisfiability (SAT) can directly benefit from this progress.In this work we present the word level framework WoLFram that enables the development of applications for formal verification of systems independent of the underlying proof technique. The framework is partitioned into an application layer, a core engine and a back-end layer. A wide range of applications is implemented, e.g. equivalence and property checking including algorithms for coverage/property analysis, debugging and robustness checking. The backend supports Boolean as well as word level techniques, like SMT and Constraint Solving (CSP). This makes WoLFram a stable backbone for the development and quick evaluation of emerging verification techniques.

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Abstract-Today, there exist powerful algorithms for automated debugging. Some of the debugging algorithms focus on fault localization while others try to explain the faulty behavior by providing, e.g., correct traces that are similar to a failure trace. SAT-based debugging locates faults, but does not explain the faulty behavior, e.g., some temporal properties of fault candidates are not fully explored.In this work, we study the resolution of SAT-based debugging with respect to its capability to locate faults and to explain faults. A strategy is presented that increases the diagnostic resolution of SAT-based debugging by combining fault localization and fault explanation in one algorithm. The experimental results confirm the strength of the approach and give directions for further research.