WoLFram- A Word Level Framework for Formal Verification

Sülflow, André; Kühne, Ulrich; Fey, Görschwin; Große, Daniel; Drechsler, Rolf

doi:10.1109/rsp.2009.21

Cited by 26 publications

(14 citation statements)

References 35 publications

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“…Modules on the word level are considered, i.e., a module may be a single gate, but also a multiplier. All experiments have been conducted on an AMD Athlon X2 processor (3 MHz, 4GB RAM) using the verification environment WoLFram [20] and the SMT solver Boolector [21].…”

Section: Resultsmentioning

confidence: 99%

Towards Unifying Localization and Explanation for Automated Debugging

Fey

Sülflow

Drechsler

2010

2010 11th International Workshop on Microprocessor Test and Verification

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Abstract-Today, there exist powerful algorithms for automated debugging. Some of the debugging algorithms focus on fault localization while others try to explain the faulty behavior by providing, e.g., correct traces that are similar to a failure trace. SAT-based debugging locates faults, but does not explain the faulty behavior, e.g., some temporal properties of fault candidates are not fully explored.In this work, we study the resolution of SAT-based debugging with respect to its capability to locate faults and to explain faults. A strategy is presented that increases the diagnostic resolution of SAT-based debugging by combining fault localization and fault explanation in one algorithm. The experimental results confirm the strength of the approach and give directions for further research.

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Section: Resultsmentioning

confidence: 99%

Towards Unifying Localization and Explanation for Automated Debugging

Fey

Sülflow

Drechsler

2010

2010 11th International Workshop on Microprocessor Test and Verification

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“…When a circuit has a single clock, and the initial states of flipflops are 0, a flipflop is denoted as b = F F (a). In our framework, a flipflop and a signal can be a word with n bits as we use a word-level model of the circuit [12].…”

Section: Bug Model-free Sat-based Debuggingmentioning

confidence: 99%

Debug Automation for Synchronization Bugs at RTL

Dehbashi

Fey

2014

2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

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Abstract-One major concern in the design of Very-LargeScale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug synchronization bugs due to coding mistakes at RTL. In particular, we introduce an appropriate bug model and show how synchronization bugs are differentiated from other types of bugs by our approach. The experimental results on LGsynth93 and ITC-99 benchmark suites and RTL modules of OpenRISC and OpenSPARC CPUs show diagnosis accuracy and efficiency of the approach.Keywords-debug automation, synchronization bug, SAT-based debugging I. INTRODUCTION Due to the increasing design size and complexity of VLSI circuits, the cost of VLSI systems verification and debugging has significantly increased. Verification tools check the correctness of a design against its specification. Upon detection of a design error, the error is returned as a counterexample. Having a counterexample, the debug process starts localizing and rectifying the bug. But this process is often a manual task which needs a large effort. Thus, automated approaches to design debugging are necessary to decrease the development cycle of VLSI products.Design bugs at RTL are classified into three major classes: logic bugs, algorithmic bugs and synchronization bugs . Algorithmic bugs can have a severe impact on the correctness of a design and they usually require multiple major modifications to be fixed. Synchronization bugs are related to synchronization of data with respect to clock cycles in a design. For most of the synchronization bugs, a signal requires to be latched a cycle earlier or a cycle later in order to keep the correct timing behavior of signals in the design [1]. The most common fix for this class of design bugs is the manual addition or removal of flipflops to satisfy the correct timing behavior of the circuit. These bug models are called missing flipflop and extra flipflop.In the pre-silicon stage, a design is verified against its specification by verification tools. A specification describes the correct timing behavior of a design. The work in [6] presents a formal method to specify the relations between multiple clocks and to model the possible behaviors. Then, a hardware design is verified against the specified clock constraints. An efficient clock modeling approach is presented in [7] to handle clock related challenges uniformly. The approach converts multiple clocks with arbitrary frequencies and ratios, gated clocks, multiple phases, latches and flip-flops in multi-clock synchronous system, into a single-clock model. Clock constraints are automatically generated to avoid unnecessary unrolling and loop-checks in Bounded Model Checking (BMC).The work in [2] presents a model based on Boolean satisfiability to automate debugging of logic bugs. A circuit is enhanced with correction block in order to find the...

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“…Open Cell Library [22]. The techniques described in this paper are implemented using C++ in the WoLFram environment [23]. For the experiments, one time unit is 0.01 ns.…”

Section: Slowdown Versus Speedupmentioning

confidence: 99%