h DEBUGGING OF SPEED-LIMITING paths (speedpaths) is a key challenge in development of very large scale integrated (VLSI) circuits as timing variations induced by process and environmental effects are increasing. This paper presents an approach to automate speedpath debugging under timing variations. First, timing behavior of a circuit and corresponding variation models are converted into a functional domain. Then, our automated debugging based on boolean satisfiability (SAT) diagnoses speedpaths. The experimental results show the effectiveness of our approach on ISCAS'85 and ISCAS'89 benchmarks suites.One of the major challenges in designing highperformance VLSI circuits is diagnosis and analysis of speedpaths. A speedpath is a frequency-limiting critical path which affects the performance of a chip [2]. A speedpath that violates timing constraints at the post-silicon stage is called failing speedpath [3]. Speedpaths fail due to, e.g., timing variations induced by process, design, and environmental effects [2].Post-silicon validation involves applying test vectors to the chip in order to verify its correct behavior. When a speed failure is detected due to frequency constraints [4], the debug team identifies failing speedpaths. But this is a time-consuming process which requires a significant effort. Thus, automated debugging approaches to identify failing speedpaths are necessary to speed up the process.Recently, there is a range of works that considers timing analysis of circuits under variations. A survey of the works focusing on statistical static timing analysis (SSTA) is given in [5]. SSTA methods analyze a circuit considering timing variations. The work in [3] proposes a formal procedure based on an integer linear programming (ILP) formulation to diagnose segments of failing speedpaths due to process variations. ILP is a specific case of a system of linear constraints in which the variables can only take integer values. The ILP-based debug approach identifies segments of failing speedpaths that have a post-silicon delay larger than their estimated delay at the pre-silicon stage. Parameterized static timing analysis (PSTA) is used in [6] to obtain a variational model for every candidate speedpath from a given set of potential candidates. These variational models are then combined to create a cost function. This PSTA-based cost function determines the likelihood of any given combination of paths to be the selection of ''true'' speedpaths. The cost function is utilized by a branch-and-bound approach to Editor's notes: This paper presents a novel approach to automate speedpath debugging taking into account variations. The proposed technique is based on Boolean Satisfiability. The approach is based on converting the timing behavior of a circuit into the functional domain, inserting a variation logic into the model, and using a Boolean Satisfiability solver to extract failing speedpaths.determine the most probable failing speedpaths. In contrast to our approach, the previous approach needs a set of user-supplied ...
Abstract-One major concern in the design of Very-LargeScale Integrated (VLSI) circuits is debugging as design size and complexity increase. Automation of the debugging process helps to decrease the development cycle of VLSI circuits and consequently to achieve a higher productivity. This paper presents an approach to automatically debug synchronization bugs due to coding mistakes at RTL. In particular, we introduce an appropriate bug model and show how synchronization bugs are differentiated from other types of bugs by our approach. The experimental results on LGsynth93 and ITC-99 benchmark suites and RTL modules of OpenRISC and OpenSPARC CPUs show diagnosis accuracy and efficiency of the approach.Keywords-debug automation, synchronization bug, SAT-based debugging I. INTRODUCTION Due to the increasing design size and complexity of VLSI circuits, the cost of VLSI systems verification and debugging has significantly increased. Verification tools check the correctness of a design against its specification. Upon detection of a design error, the error is returned as a counterexample. Having a counterexample, the debug process starts localizing and rectifying the bug. But this process is often a manual task which needs a large effort. Thus, automated approaches to design debugging are necessary to decrease the development cycle of VLSI products.Design bugs at RTL are classified into three major classes: logic bugs, algorithmic bugs and synchronization bugs . Algorithmic bugs can have a severe impact on the correctness of a design and they usually require multiple major modifications to be fixed. Synchronization bugs are related to synchronization of data with respect to clock cycles in a design. For most of the synchronization bugs, a signal requires to be latched a cycle earlier or a cycle later in order to keep the correct timing behavior of signals in the design [1]. The most common fix for this class of design bugs is the manual addition or removal of flipflops to satisfy the correct timing behavior of the circuit. These bug models are called missing flipflop and extra flipflop.In the pre-silicon stage, a design is verified against its specification by verification tools. A specification describes the correct timing behavior of a design. The work in [6] presents a formal method to specify the relations between multiple clocks and to model the possible behaviors. Then, a hardware design is verified against the specified clock constraints. An efficient clock modeling approach is presented in [7] to handle clock related challenges uniformly. The approach converts multiple clocks with arbitrary frequencies and ratios, gated clocks, multiple phases, latches and flip-flops in multi-clock synchronous system, into a single-clock model. Clock constraints are automatically generated to avoid unnecessary unrolling and loop-checks in Bounded Model Checking (BMC).The work in [2] presents a model based on Boolean satisfiability to automate debugging of logic bugs. A circuit is enhanced with correction block in order to find the...
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