Impact of resistive paths on NVM array reliability: Application to Flash &amp; ReRAM memories

Canet, P.; Postel-Pellerin, J.; Aziza, Hassen

doi:10.1016/j.microrel.2016.07.096

Cited by 5 publications

(4 citation statements)

References 7 publications

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“…The principle operation of OxRAM based memory cells consists of several stages [17]. The first step is the Forming operation which is executed (3) [18]. After Forming, the cell can be switched between HRS and LRS by applying specific voltages across the electrodes of the OxRAM cell (i.e.…”

Section: T1r Structurementioning

confidence: 99%

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Non-volatile SRAM memory cells based on ReRAM technology

et al. 2020

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Static Random-Access Memories (SRAMs) are very common in today's chip industry due to their speed and power consumption but are classified as volatile memories. Non-volatile SRAMs (nvSRAMs) combine SRAM features with nonvolatility. This combination has the advantage to retain data after power off or in the case of power failure, enabling energy-efficient and reliable systems under frequent power-off conditions. In this work, several nvSRAMs architectures based on Oxide Random-Access Memory (OxRAM) technology are presented and compared. OxRAMs are non-volatile memories considered as a subset of Resistive RAM (ReRAM) technology.

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Section: T1r Structurementioning

confidence: 99%

“…The energy dissipated by the OxRAM device during Forming is 1.7 nJ. 7T1R [29] and 8T2R [30] nvSRAM cells are based on 6T SRAM core unlike 4T2R cell [18]. Although 7T1R cell [29] suffers from a slight increase of the variability in resistance and process, but this issue does not corrupt the normal operation of the nvSRAM design.…”

Section: T2r Cell [32]mentioning

confidence: 99%

Non-volatile SRAM memory cells based on ReRAM technology

et al. 2020

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“…Narrow programming pulses are possible due to the excellent high speed switching characteristic of the OxRAM cell. This programming strategy allows an optimal control of the programmed resistance despite the intrinsic cell variability [7] [8]. The approach to use memristors in programmable analog circuits was suggested in [9].…”

Section: Introductionmentioning

confidence: 99%

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

Aziza

Dufaza

Perez

et al. 2019

J CIRCUIT SYST COMP

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This paper introduces memristor-based operational amplifiers (OpAmps) in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop OpAmps. An inverting OpAmp, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area.

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“…Finally memory array organization itself may have also an impact on memory cell variability. With the cell area reduction and the increase of the memory cut capacity, voltage drop along bitlines and wordlines are of great concerns for designers [15]. The use of metal straps compensates efficiently the voltage drop but breaks the regularity of the array layout with possible side effect.…”

Section: Introductionmentioning

confidence: 99%

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

Kempf¹,

Marca²,

Baron³

et al. 2018

2018 IEEE International Reliability Physics Symposium (IRPS)

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The reliability requirements of Flash memory become more and more challenging. Flash memory technology development needs testchips to allow large statistical studies and a product-like approach. In this paper, we present a methodology of bitmap analysis to extract and follow the intrinsic and extrinsic parameters of a 40nm eFlash technology during ramp-up. This methodology is based first on analog bitmap acquisition on 512kB testchip, followed by correction of spatial variabilities like peripheral circuit influences, array organization impacts and process-induced effects, to extract supplementary cell electrical parameters such as threshold voltage, transconductance or programing window. Finally such an analysis tool enhances the advantageous properties of test chip, its large memory cell statistics and its product-like organization, to give more reliable data and yields more information about intrinsic cell technology weaknesses and the best way to tackle them when integrated at product level. I. Criteria Test structure Single device Test chip Statistics availability Low bits density High bits density Cell envirronement Limited Product like Memory defectivity Memory only Peripheral effect, memory array organization/ intersite variation Test time Low Need burn-in, or early failure binning (EWS) Test flexibility High. Limited by its embedded test modes (BIST, reliability test, DMA…) and register values.

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Impact of resistive paths on NVM array reliability: Application to Flash & ReRAM memories

Cited by 5 publications

References 7 publications

Non-volatile SRAM memory cells based on ReRAM technology

Non-volatile SRAM memory cells based on ReRAM technology

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip

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