Non-volatile SRAM memory cells based on ReRAM technology

Bazzi, Hussein; Harb, Ahmad; Aziza, Hassen; Moreau, Mathieu

doi:10.1007/s42452-020-03267-z

Cited by 8 publications

(5 citation statements)

References 36 publications

(53 reference statements)

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“…Te reuse of bit lines leads to the increase of parasitic capacitance, which increases the read delay of memory cell. In Reference [20], the upper electrode of RRAM is connected to drain, and the lower electrode is led out as a control signal. Te high forming voltage will lead to high punch through voltage, which may damage the transistors.…”

Section: Resultsmentioning

confidence: 99%

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Yin

Liao

Chen

2023

Active and Passive Electronic Components

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Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.

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Section: Resultsmentioning

confidence: 99%

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

Yin

Liao

Chen

2023

Active and Passive Electronic Components

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“…Figure 12(a) which reveals that at −40 • C, 'store-1' consumes 0.721 fJ, whereas at 27 • C and at 120 • C, it consumes 0.842 fJ and 0.993 fJ, respectively. As the temperature increases, the energy consumption increases because of faster switching rates [47][48][49]. However, 'restore-1' experiences an increase in energy consumption of 36.08% and 69.07% at 27 • C and 120 • C compared to −40 • C, with energy of 3.428 fJ at −40 • C as shown in figure 12(b).…”

Section: Temperature Dependent Read Current For Various Process Cornersmentioning

confidence: 98%

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

Chakraborty,

Majumder,

Debbarma

et al. 2024

Semicond. Sci. Technol.

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This research investigates, for the first time, a novel eight-transistor-two-memristor (8T2M) nonvolatile static random access memory (NVSRAM) with 7-nm technology. The key innovation in this design lies in the incorporation of multiple-threshold complementary metal oxide semiconductor (MTCMOS) technology with power gating technique, which enables efficient power management and enhanced performance with low leakage current. The implementation of multiple threshold voltage levels allows for dynamic control of transistor behavior, optimizing power consumption and read/write speeds. As compared to a traditional six-transistor (6T) static random access memory (SRAM) cell, it has been ascertained that there is a 33% enhancement in the read margin and an 18% improvement in the write margin. Moreover, the delay for read, write ‘0’ and write ‘1’ is also minimized by 63.89%, 37.99% and 42.77%. Furthermore, the power attenuation is also reduced for read and write by 63.02% and 81.6%, respectively with respect to a conventional SRAM.

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“…A major goal of nvSRAM is to have a minimal impact on SRAM’s fundamental structure. While many nvSRAMs have been presented, including 4T2R, 7T1R, and 8T2R, herein, 7T1R [ 21 ] is leveraged.…”

Section: Introductionmentioning

confidence: 99%

Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study

Taheri,

Tabrizchi,

Roohi

2024

Micromachines

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This paper conducts a comprehensive study on intermittent computing within IoT environments, emphasizing the interplay between different dataflows—row, weight, and output—and a variety of non-volatile memory technologies. We then delve into the architectural optimization of these systems using a spatial architecture, namely IDEA, with their processing elements efficiently arranged in a rhythmic pattern, providing enhanced performance in the presence of power failures. This exploration aims to highlight the diverse advantages and potential applications of each combination, offering a comparative perspective. In our findings, using IDEA for the row stationary dataflow with AlexNet on the CIFAR10 dataset, we observe a power efficiency gain of 2.7% and an average reduction of 21% in the required cycles. This study elucidates the potential of different architectural choices in enhancing energy efficiency and performance in IoT systems.

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Non-volatile SRAM memory cells based on ReRAM technology

Cited by 8 publications

References 36 publications

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node

A novel MTCMOS based 8T2M NVSRAM design for low power applications with high temperature endurance

Intermittent-Aware Design Exploration of Systolic Array Using Various Non-Volatile Memory: A Comparative Study

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