Impact of data cache memory on the single event upset-induced error rate of microprocessors

Abstract

Cache memories embedded in most of complex processors significantly contribute to the global single event upset-induced error rate. Three different approaches allowing the study of this contribution by fault injection are investigated in this paper

Balancing Performance and Reliability in the Memory Hierarchy

“…Since it is difficult to provide guaranteed reliability for caches, caches are often disabled in safety-critical applications [4]. By disabling the cache, the area susceptible to SEUs is drastically reduced and so the processor's dependability is dramatically increased.…”

“…Most previously proposed reliability estimation methods for cache memories have been based on fault injection (FI) strategies [4,8,14,22]. When using a FI strategy, a limited number of memory addresses are targeted.…”

An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors

“…All data generated by the sensor had a maximum range of about 2 meters with an accuracy of about one centimeter, so at least 3 magnitude bits and 7 fractional bits are required. In particular, fx [13]. [3] is insufficient to accurately represent all the fractional bits, which is also reflected by elevated fault-free RMSE.…”

“…[3] 0 [4]. [28] 0.021 0.021 0 0.022 0 0.021 0 fx32 [13]. [19] 0.021 0.021 0 0.024 2 0.021 1 fx16 [4].…”

“…Ongil et al [20] discuss various types of fault injection techniques for medium-size non-programmable circuits. In [14], these techniques are applied to the Leon 2 processor and compared with the software-based code-emulated upsets method [13].…”