Balancing Performance and Reliability in the Memory Hierarchy

Asadi, Hossein; Sridharan, Vilas; Tahoori, Mehdi B.; Kaeli, David

doi:10.1109/ispass.2005.1430581

Cited by 93 publications

(55 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since soft errors induced during the vulnerable phases in the data cache only present the potential to crash the execution or the lower memory hierarchies, TVF defines the upper bound on AVF and can be estimated more accurately than AVF. Further, TVF is also different from the critical time [15] in that the critical time is calculated based on the word-level vulnerability analysis while TVF is derived from a flexible lifetime model for detailed vulnerability analysis at various granularities, e.g., a cacheline, a word, or a byte.…”

Section: Tvfmentioning

confidence: 99%

“…Such a study could provide enough insight into cache reliability behavior, which the designer could take advantage of to design highly costeffective reliable caches. Recent papers [8], [9], [10], [1], [15], [16] present some initial efforts toward such a cache vulnerability analysis. However, their cacheline-or wordbased vulnerability characterization used some simple generation model [17] that could not explore the temporal vulnerability of the cache, i.e., how different lifetime phases of the cache data contribute to vulnerability.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

Wang

Ziavras

2009

IEEE Trans. Comput.

View full text Add to dashboard Cite

Abstract-Soft errors induced by energetic particle strikes in on-chip cache memories have become an increasing challenge in designing new generation reliable microprocessors. Previous efforts have exploited information redundancy via parity/ECC codings or cacheline duplication for information integrity in on-chip cache memories. Due to various performance, area/size, and energy constraints in various target systems, many existing unoptimized protection schemes may eventually prove significantly inadequate and ineffective. In this paper, we propose a new framework for conducting comprehensive studies and characterization on the reliability behavior of cache memories, in order to provide insight into cache vulnerability to soft errors as well as design guidance to architects for highly efficient reliable on-chip cache memory design. Our work is based on the development of new lifetime models for data and tag arrays residing in both the data and instruction caches. Those models facilitate the characterization of cache vulnerability of stored items at various lifetime phases. We then exemplify this design methodology by proposing reliability schemes targeting at specific vulnerable phases. Benchmarking is carried out to showcase the effectiveness of our approach.

show abstract

Section: Tvfmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

Wang

Ziavras

2009

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…Transient fault model Transient faults within the cache are mainly caused by alpha particles hitting the flip-flops of the cache [9,17]. The physical procedure of the particle-hits causing faults is complex and the effect depends on many factors, like the energy transferred from the particle into the circuit, the transistor size, etc.…”

Section: Preliminariesmentioning

confidence: 99%

“…Cache reliability is mainly threatened by transient faults, caused by strikes from alpha particles and energetic particles [9]. When a memory cell (flip-flop) is hit by such a particle, though the circuit itself is not damaged, the stored bit value can flip and cause an error.…”

Section: Introductionmentioning

confidence: 99%

Cache size selection for performance, energy and reliability of time-constrained systems

Cai

Schmitz

Ejlali

et al. 2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

View full text Add to dashboard Cite

Abstract-Improving performance, reducing energy consumption and enhancing reliability are three important objectives for embedded computing systems design. In this paper, we study the joint impact of cache size selection on these three objectives. For this purpose, we conduct extensive fault injection experiments on five benchmark examples using a cycle-accurate processor simulator. Performance and reliability are analyzed using the performability metric. Overall, our experiments demonstrate the importance of a careful cache size selection when designing energy-efficient and reliable systems. Furthermore, the experimental results show the existence of optimal or Pareto-optimal cache size selection to optimize the three design objectives.

show abstract

“…For cache flusing, the operating system or the hardware flushes the cache to reduce its vulnerable lifetime, resulting in lower AVFs [87,88].…”

Section: Hardware Techniquesmentioning

confidence: 99%

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

Dey

View full text Add to dashboard Cite

Chip-multiprocessors (CMPs) have become ubiquitous in modern computing and the mainstream architecture for various platforms, including laptops, desktops, and large server machines. As technology scaling continues and more transistors are accommodated on the chip, the number of cores on CMPs is growing, and multi-core machines are scaling up to many-core machines. With this multi-core scaling, two major problems arise: shared-resource contention and soft errors or transient faults. Shared-resource contention can degrade an application's performance significantly, and soft errors increase the probability of incorrect application execution and the production of visible errors. To realize the full potential of multi-and many-core platforms, it is critical to ensure that applications in a workload not only execute e ciently and fast, but also correctly.In this dissertation, we develop a novel, general, and unified framework, ReSense, to address several challenges on multicore architectures including performance optimization, reliability improvement, power and thermal management. The framework includes five components: a general characterization methodology, a characterization metric, a sensitivity score, a thread mapping algorithm, and a run-time system. An instance of the framework is applied in two phases: characterization and mapping. The characterization phase utilizes the general characterization methodology and characterization metric to identify application characteristics without considering any co-runner(s). It generates a resource-sensitivity score for each application in a workload. In the mapping phase, the run-time system uses a thread-mapping algorithm and the sensitivity scores of the applications in a workload to c Abstract d determine the thread-mappings that optimize the objective function of the targeted problem.To demonstrate the utility and e ectiveness of ReSense, we use it to address the problems of shared-resource contention and soft errors for multi-threaded applications. For the resource contention problem, the characterization methodology determines how a multi-threaded application's performance is a ected as it shares a resource in the memory hierarchy. A sensitivity score based on resource contention is produced for each application in a workload.The run-time system uses the resource-contention sensitivity scores and a thread-mapping algorithm to allocate threads from a workload to core to mitigate shared-resource contention, thus improving response time and throughput.For the soft error problem, the characterization methodology determines how a multithreaded application's vulnerability to soft errors in shared caches is a ected by its resource occupancy duration. A sensitivity score based on cache occupancy is produced for each application in a workload. The run-time system uses the cache-occupancy sensitivity scores and a thread-mapping algorithm to allocate workload threads to cores to reduce the occupancy in the shared caches, thus reducing cache vulnerability.Both minimizing...

show abstract

Balancing Performance and Reliability in the Memory Hierarchy

Abstract: Abstract

Cited by 93 publications

References 29 publications

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

On the Characterization and Optimization of On-Chip Cache Reliability against Soft Errors

Cache size selection for performance, energy and reliability of time-constrained systems

ReSense: A Unified Framework for Improving Performance and Reliability in Multicore Architectures

Contact Info

Product

Resources

About