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Nanoscale electronics is increasingly affected by disturbances caused by radiation, noise and effects of statistical process variations. Moreover, deliberate injection of faults into cryptographic circuits is used by malicious attackers to perform cryptanalysis and gain access to sensitive information. Error-detecting codes are employed to protect circuits against such disturbances, and new advanced codes specifically designed to counter malicious attacks have recently been introduced. However, a number of logic gates in the circuit are not adequately protected by the error-detecting code, as faults affecting these gates escape detection with a relatively high probability. We introduce a cross-level protection solution, where a light-weight error-detecting code is combined with hardening of insufficiently protected gates using transistor resizing. Such gates are determined by FPGA-supported fault injection. A thorough electrical analysis is performed in order to modify the electrical parameters of these gates such that faults are highly unlikely. We report area and power overhead for a number of error-detecting codes. To the best of our knowledge, this is the first work which co-optimizes fault handling by information redundancy based on error-detecting codes and by hardening individual circuit elements.

Vulnerability to malicious fault attacks is an emerging concern for hardware circuits that are employed in mobile and embedded systems and process sensitive data. We describe a new methodology to assess the vulnerability of a circuit to such attacks, taking into account built-in protection mechanisms. Our method is based on accurate modeling of fault effects and detection status expressed by Boolean satisfiability (SAT) formulas. Vulnerability is quantified based on the number of solutions of these formulas, which are determined by an efficient #SAT solver. We demonstrate the applicability of this method for design space exploration of a pseudo random number generator and for calculating the attack success rate in a multiplier circuit protected by robust error-detecting codes.Index Terms-Error detection, fault attacks, random number generators, satisfiability (SAT), vulnerability analysis.

Abstract-State-of-the-art cyber-physical systems are increasingly deployed in harsh environments with non-negligible soft error rates, such as aviation or search-and-rescue missions. State-of-the-art nanoscale manufacturing technologies are more vulnerable to soft errors. In this paper, we present an FPGAbased framework for injecting soft errors into user-specified memory elements of an entire microprocessor (MIPS32) running application software. While the framework is applicable to arbitrary software, we demonstrate its usage by characterizing soft errors effects on several software filters used in aviation for probabilistic sensor data fusion.

Multiantenna telecommunication systems represent channels with multiple inputs and multiple outputs (MIMO) by matrices. QR decomposition (QRD) of the channel matrix is a crucial part of MIMO detection algorithms, such as successive interference cancellation or sphere detection. Modern standards like Long Term Evoliton (LTE) require the processing of millions of matrices per second, in order to compensate channel changes that occur due to the mobility of the detector and Doppler spread. We introduce a new architecture for minimum mean square error (MMSE) sorted QR decomposition based on Givens rotations. The architecture is derived from classical systolic array approach but includes modifications to allow sorting and MMSE preprocessing. It balances throughput against area and fulfills the real-time requirements of 1.763 µs and 0.881 µs derived from the LTE MIMO standard when synthesized on ALTERA Stratix III and Stratix V family FPGAs. Moreover, it can trade speed for area and is suitable for tighter time constraints.

Reliability of modern MIMO receiver hardware becomes a critical issue due to recent advantages in semiconductor technology and continuous transistor size shrinkage. Most of the research conducted so far, analyzed the impact of solely memory errors on the performance of receivers' individual components (e.g. decoders) and on the system level performance of the whole receiver in terms of Frame Error Rate (FER). This paper presents the first reliability analysis of critical channel preprocessing block of the receiver. The reliability of individual computational submodules of channel preprocessing is assessed by gate level FPGAbased fault injection. The most unreliable sub-module is identified as the boundary cell, yielding the most performance degradation by introducing the FER floor of 10 −3 for SNR value of 10 dB for very low fault injection rate. Within the boundary cell, the inverse square root is identified as least critical.

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