Cross-level protection of circuits against faults and malicious attacks

Abstract

Nanoscale electronics is increasingly affected by disturbances caused by radiation, noise and effects of statistical process variations. Moreover, deliberate injection of faults into cryptographic circuits is used by malicious attackers to perform cryptanalysis and gain access to sensitive information. Error-detecting codes are employed to protect circuits against such disturbances, and new advanced codes specifically designed to counter malicious attacks have recently been introduced. However, a number of logic gates in the circuit are not adequately protected by the error-detecting code, as faults affecting these gates escape detection with a relatively high probability. We introduce a cross-level protection solution, where a light-weight error-detecting code is combined with hardening of insufficiently protected gates using transistor resizing. Such gates are determined by FPGA-supported fault injection. A thorough electrical analysis is performed in order to modify the electrical parameters of these gates such that faults are highly unlikely. We report area and power overhead for a number of error-detecting codes. To the best of our knowledge, this is the first work which co-optimizes fault handling by information redundancy based on error-detecting codes and by hardening individual circuit elements.

Formal Vulnerability Analysis of Security Components

“…We used a small combinational Braun 4 × 4 multiplier circuit [47] protected by the information redundancy scheme such as in [48] to evaluate our flow for combinational circuits. The combinational core is equipped with a check bit predictor and a consistency checker according to an EDC.…”

“…The combinational core is equipped with a check bit predictor and a consistency checker according to an EDC. As in [48], four codes have been considered: 1) one linear (parity) code and 2) three nonlinear quadratic-sum robust codes over GF(2), GF(4), and GF(16) [23], respectively. ASR has been estimated in [48] by an FPGA-assisted fault-injection experiment while the results reported here are exact and have been determined by the #SAT-based flow.…”

“…As in [48], four codes have been considered: 1) one linear (parity) code and 2) three nonlinear quadratic-sum robust codes over GF(2), GF(4), and GF(16) [23], respectively. ASR has been estimated in [48] by an FPGA-assisted fault-injection experiment while the results reported here are exact and have been determined by the #SAT-based flow. Note that the circuit in [48] has been resynthesized using only inverters, NAND2 and NOR2 gates to facilitate electrical analysis performed in that work, so that the gate-level net-lists are not identical and the results are not directly comparable.…”

“…ASR has been estimated in [48] by an FPGA-assisted fault-injection experiment while the results reported here are exact and have been determined by the #SAT-based flow. Note that the circuit in [48] has been resynthesized using only inverters, NAND2 and NOR2 gates to facilitate electrical analysis performed in that work, so that the gate-level net-lists are not identical and the results are not directly comparable. Table I contains results for the four versions of the Braun multiplier considering single and double attacks.…”

Hardware security and test: Friends or enemies?

“…A special class of non-linear robust codes with guaranteed minimal probability of adversarial attacks has been investigated in [24]. The application of robust codes in actual circuits requires a better understanding of the relationship between informationtheoretical bounds known for such EDC and their effects in actual circuits [25].…”