Protecting cryptographic hardware against malicious attacks by nonlinear robust codes

Tomashevich, Victor; Neumeier, Yaara; Kumar, Raghavan; Keren, Osnat; Polian, Ilia

doi:10.1109/dft.2014.6962084

Cited by 18 publications

(16 citation statements)

References 15 publications

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“…A subset of r bits in the LFSR of a given design (e.g. 35 16 ), determined during design time, is used to encode the error signals for the CED checker. This subset can be chosen arbitrarily since the characteristic polynomial and seed of the LFSR are programmable.…”

Section: E Error Signal Encodingmentioning

confidence: 99%

“…If the error signal takes any other value (e.g. 36 16 ), an attack is detected. The subset of r bits can be different for different chip designs.…”

Section: E Error Signal Encodingmentioning

confidence: 99%

“…The decoding process checks for attacks at the outputs of the sender as well as attacks at its own inputs. Suppose that, primary inputs (e.g., FA 16 ) and input check bits (e.g., 1 16 ) are received. The input check bits are then XOR-ed with the previous cycle's input check bits (e.g., B 16 ) to calculate the expected randomized parity bits (e.g.…”

Section: B Input Decodingmentioning

confidence: 99%

“…The input check bits are then XOR-ed with the previous cycle's input check bits (e.g., B 16 ) to calculate the expected randomized parity bits (e.g. 1 16 ⊕ B 16 =A 16 ). The actual randomized parity bits are calculated from the primary inputs (e.g., A 16 ).…”

Section: B Input Decodingmentioning

confidence: 99%

“…5. Error-detecting codes [16] can be compromised if the code construction is known. T This paper presents a Trojan Prevention and Detection (TPAD) architecture for digital systems.…”

mentioning

confidence: 99%

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TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

Ganesan

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-There are increasing concerns about possible malicious modifications of integrated circuits (ICs) used in critical applications. Such attacks are often referred to as hardware Trojans. While many techniques focus on hardware Trojan detection during IC testing, it is still possible for attacks to go undetected. Using a combination of new design techniques and new memory technologies, we present a new approach that detects a wide variety of hardware Trojans during IC testing and also during system operation in the field. Our approach can also prevent a wide variety of attacks during synthesis, place-and-route, and fabrication of ICs. It can be applied to any digital system, and can be tuned for both traditional and split-manufacturing methods. We demonstrate its applicability for both ASICs and FPGAs. Using fabricated test chips with Trojan emulation capabilities and also using simulations, we demonstrate: 1. The area and power costs of our approach can range between 7.4-165% and 0.07-60%, respectively, depending on the design and the attacks targeted; 2. The speed impact can be minimal (close to 0%); 3. Our approach can detect 99.998% of Trojans (emulated using test chips) that do not require detailed knowledge of the design being attacked; 4. Our approach can prevent 99.98% of specific attacks (simulated) that utilize detailed knowledge of the design being attacked (e.g., through reverse-engineering). 5. Our approach never produces any false positives, i.e., it does not report attacks when the IC operates correctly. I. INTRODUCTION HERE is growing concern about the trustworthiness of integrated circuits (ICs). If an untrusted party fabricates an IC, there is potential for an adversary to insert a malicious hardware Trojan [1], an unauthorized modification of the IC resulting in incorrect functionality and/or sensitive data being exposed [2]. These include (but are not limited to) [3]: a) Modification of functional behavior through logic changes: Index TermsFor example, extra logic gates may be inserted to force an incorrect logic value on a wire at some (arbitrary) point in time (Fig. 1a) [2]. b) Electrical modification: For example, extra capacitive loading may be placed on a circuit path to alter timing characteristics of the IC (Fig. 1b) [2]. c) Reliability degradation: For example, aging of transistors (e.g., Negative Bias Temperature Instability (NBTI)) may be accelerated, degrading reliability ( Fig. 1c) [4]. A hardware Trojan is detected when we report malicious modifications to an IC. A hardware Trojan is prevented when Manuscript received January 9, 2015; revised May 8, 2015; accepted July 20, 2015. Work supported by IARPA Trusted Integrated Chips (TIC) Program. All authors are with Dept. of Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: tonyfwu@stanford.edu). S. Mitra is also with Dept. of Computer Science, Stanford University.we stop a hardware Trojan from being inserted. Part of the challenge in detecting or preventing hardware Trojans arises from the fact that...

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Section: E Error Signal Encodingmentioning

confidence: 99%

“…If the error signal takes any other value (e.g. 36 16 ), an attack is detected. The subset of r bits can be different for different chip designs.…”

Section: E Error Signal Encodingmentioning

confidence: 99%

Section: B Input Decodingmentioning

confidence: 99%

Section: B Input Decodingmentioning

confidence: 99%

“…5. Error-detecting codes [16] can be compromised if the code construction is known. T This paper presents a Trojan Prevention and Detection (TPAD) architecture for digital systems.…”

mentioning

confidence: 99%

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