Impact Ionization MOS (I-MOS)—Part I: Device and Circuit Simulations

Abstract

Abstract-One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and ON 1 mA m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.Index Terms-Avalanche, avalanche photodiode (APD), gate control of impact ionization, impact-ionization avalanche transit-time (IMPATT), germanium, hot carriers, impactionization (I-MOS), kT/q, low static power, modulated breakdown, MOSFET, nonlinearity, p-i-n, silicon, subthreshold slope, 5 mV/dec.

Charge Trapping Mechanism Leading to Sub-60-mV/decade-Swing FETs

“…This inherent scaling limit has triggered the investigation of various alternative device technologies and principles. The alteration of the channel conduction mechanism has been facilitated in tunnel-FETs [2], [3] and impact-ionization-FETs [4]. Other approaches target gate-amplification in suspended-gate structures [5], [6] or with ferroelectric materials [7]- [9].…”

Impact ionization rate in direct gap semiconductors

“…Рис. 1), лежит в основе функ-ционирования большого семейства устройств современной электроники, таких как лавинно-пролетные диоды (IMPATT), лавинные фотоприемники (APD) [1], а также транзисторы с полевым контролем ударной ионизации (I-MOS) [2], в которых экс-периментально достигнута крутизна подпороговой части ВАХ на уровне 5 mV/dec при T=400 K, что позволяет в разы увеличить скорость переключения. С точки зре-ния эффективности применения ударной ионизации в качестве физического принципа работы приборов наиболее удачным является использование в качестве областей ла-винного умножения рассматриваемых в данной работе прямозонных полупроводников с относительно небольшой шириной запрещенной зоны E g 1 eV, в которых энер-гетический порог лишь немного отличается от величины щели: E th ≈ E g (1 + 2µ) [3], где µ = m e /m hh ≪ 1.…”

Tunneling Field-Effect Transistors for Ultra-Low-Power Application

“…To reduce the subthreshold swing below 60 mV/decade at room temperature, various carrier injection mechanisms other than thermal carrier injection have been proposed [2][3][4][5][6][7][8][9][10][11]. Interband tunneling can be used for injection of carriers and the device that utilizes such a mechanism is a tunneling field-effect transistor (TFET) [12][13][14][15][16].…”