We survey the current state of phase change memory (PCM), a non-volatile solid-state memory technology built around the large electrical contrast between the highly-resistive amorphous and highly-conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance and yield characteristics. We introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. We then address challenges for the technology, including the design of PCM cells for low RESET current, the need to control device-to-device variability, and undesirable changes in the phase change material that can be induced by the fabrication procedure. We then turn to issues related to operation of PCM devices, including retention, device-to-device thermal crosstalk, endurance, and bias-polarity effects. Several factors that can be expected to enhance PCM in the future are addressed, including Multi-Level Cell technology for PCM (which offers higher density through the use of intermediate resistance states), the role of coding, and possible routes to an ultra-high density PCM technology.Comment: Review articl

Storage-class memory (SCM) combines the benefits of a solidstate memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitrideoxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

We have demonstrated symmetrically high levels of electrical activation of both p- and n-type dopants in germanium. Rapid thermal annealing of various commonly implanted dopant species were performed in the temperature range of 600–850 °C in germanium substrates. Diffusion studies were also carried out by using different anneal times and temperatures. T-SUPREM™ simulations were used to fit the experimental profiles and to extract the diffusion coefficient of various dopants.

One of the "fundamental" problems in the continued scaling of MOSFETs is the 60 mV/decade room temperature limit in subthreshold slope. In this paper, we report initial studies on a new kind of transistor, the I-MOS. The I-MOS uses modulation of the breakdown voltage of a gated p-i-n structure in order to switch from the OFF to the ON state and vice versa. Since impact-ionization is an abrupt function of the electric field (or the carrier energy), simulations show that the device has a subthreshold slope much lower than kT/q. Simulations also show that it is indeed possible to make complementary circuits with switching speeds comparable to or exceeding CMOS. Experimental results on a silicon based prototype verify the basic concept and show very steep subthreshold slopes with high speed turn-on and turn-off, Lower bandgap materials are also being investigated to reduce the value of the breakdown voltage and permit lower voltage operation.

Abstract-One of the fundamental problems in the continued scaling of transistors is the 60 mV/dec room temperature limit in the subthreshold slope. In part I this work, a novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. The I-MOS uses gated-modulation of the breakdown voltage of a p-i-n diode to switch from the OFF state to the ON state and vice-versa. Device simulations using MEDICI show that the I-MOS has a subthreshold slope of 5 mV/dec or lower and ON 1 mA m at 400 K. Simulations were used to further explore the characteristics of the I-MOS including the transients of the turn-on mechanism, the short-channel effect, scalability, and other important device attributes. Circuit mode simulations were also used to explore circuit design using I-MOS devices and the design of an I-MOS inverter. These simulations indicated that the I-MOS has the potential to replace CMOS in high performance and low power digital applications. Part II of this work focuses on I-MOS experimental results with emphasis on hot carrier effects, germanium p-i-n data and breakdown in recessed structure devices.Index Terms-Avalanche, avalanche photodiode (APD), gate control of impact ionization, impact-ionization avalanche transit-time (IMPATT), germanium, hot carriers, impactionization (I-MOS), kT/q, low static power, modulated breakdown, MOSFET, nonlinearity, p-i-n, silicon, subthreshold slope, 5 mV/dec.

The memory capacity, computational power, communication bandwidth, energy consumption, and physical size of the brain all tend to scale with the number of synapses, which outnumber neurons by a factor of 10,000. Although progress in cortical simulations using modern digital computers has been rapid, the essential disparity between the classical von Neumann computer architecture and the computational fabric of the nervous system makes large-scale simulations expensive, power hungry, and time consuming. Over the last three decades, CMOS-based neuromorphic implementations of “electronic cortex” have emerged as an energy efficient alternative for modeling neuronal behavior. However, the key ingredient for electronic implementation of any self-learning system—programmable, plastic Hebbian synapses scalable to biological densities—has remained elusive. We demonstrate the viability of implementing such electronic synapses using nanoscale phase change devices. We introduce novel programming schemes for modulation of device conductance to closely mimic the phenomenon of Spike Timing Dependent Plasticity (STDP) observed biologically, and verify through simulations that such plastic phase change devices should support simple correlative learning in networks of spiking neurons. Our devices, when arranged in a crossbar array architecture, could enable the development of synaptronic systems that approach the density (∼10 11 synapses per sq cm) and energy efficiency (consuming ∼1pJ per synaptic programming event) of the human brain.

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