I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q

Gopalakrishnan, Kailash; Griffin, P.B.; Plummer, J.D.

doi:10.1109/iedm.2002.1175835

Cited by 263 publications

(143 citation statements)

References 7 publications

Supporting

Mentioning

132

Contrasting

Order By: Relevance

“…4 In recent years, numerous studies have examined various approaches to overcome this limit of 60 mV/dec. [4][5][6][7][8] Of these, two approaches are considered the most promising. One is the use of tunneling FET, an ambipolar device in principle that exhibits a p-type behavior with dominant hole conduction and an n-type behavior with dominant electron conduction.…”

Section: Introductionmentioning

confidence: 99%

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

Wang

Chen

et al. 2017

npj 2D Mater Appl

View full text Add to dashboard Cite

Conventional field-effect transistors (FETs) are not expected to satisfy the requirements of future large integrated nanoelectronic circuits because of these circuits' ultra-high power dissipation and because the conventional FETs cannot overcome the subthreshold swing (SS) limit of 60 mV/decade. In this work, the ordinary oxide of the FET is replaced only by a ferroelectric (Fe) polymer, poly(vinylidene difluoride-trifluoroethylene) (P(VDF-TrFE)). Additionally, we employ a two-dimensional (2D) semiconductor, such as MoS 2 and MoSe 2 , as the channel. This 2D Fe-FET achieves an ultralow SS of 24.2 mV/dec over four orders of magnitude in drain current at room temperature; this sub-60 mV/dec switching is derived from the Fe negative capacitance (NC) effect during the polarization of ferroelectric domain switching. Such 2D NC-FETs, realized by integrating of 2D semiconductors and organic ferroelectrics, provide a new approach to satisfy the requirements of next-generation low-energy-consumption integrated nanoelectronic circuits as well as the requirements of future flexible electronics.

show abstract

Section: Introductionmentioning

confidence: 99%

Two-dimensional negative capacitance transistor with polyvinylidene fluoride-based ferroelectric polymer gating

Wang

Chen

et al. 2017

npj 2D Mater Appl

View full text Add to dashboard Cite

show abstract

“…Ferroelectric gate materials [49] have been proposed to leverage an effective negative oxide capacitance to magnify channel surface potential modulation with gate voltage; although tantalizing, such an effect has yet to be confirmed experimentally. Very steep subthreshold characteristics have been demonstrated [50], [51] using nonthermionic mechanisms based on impact ionization or positive feedback, but these devices require large (> 1 V) sourceto-drain biases and suffer from fundamental drawbacks in switching speed and reliability. The most promising steep subthreshold slope devices appear to be tunneling transistors, which operate via the principle of gate-controlled band-to-band tunneling.…”

Section: B Sub-60 Mv/decade Inverse Subthreshold Slope Tunneling Fetsmentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

View full text Add to dashboard Cite

| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

show abstract

“…Sub 60mV/decade value of subthreshold swing is possible for these two modes of carrier transport [4]. The impact ionization MOSFET appeared to be very promising due to its near ideal switching characteristics [5]. But problems like threshold voltage shift caused by hot carrier injection, non-rail to rail voltage swings, and high operating voltage requirements will arise in Impact ionization MOSFETS [2].…”

Section: Introductionmentioning

confidence: 99%