IEEE P1500-compliant test wrapper design for hierarchical cores

Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips

“…In comparison, only a limited amount of work has been done on wrapper design and TAM optimization for hierarchical SOCs. Recently in [8], the issue of wrapper design for hierarchical cores has been addressed, and in [9,12,13], wrapper design and TAM optimization techniques for hierarchical cores have been explored.…”

“…In this paper, and in [8], the use of the wrapper cell configuration of Figure 1(b) is assumed. For a hierarchical core, suppose that the parent core and the child cores are tested on different TAM partitions.…”

“…For a hierarchical core, suppose that the parent core and the child cores are tested on different TAM partitions. When the parent core is in the INTEST mode, the embedded child cores have to be in EXTEST mode to ensure complete internal testing of the parent core [8,9]. Thus, the parent and the child INTEST testing cannot be done concurrently, since the child cores cannot be configured simultaneously in INTEST and EXTEST mode.…”

“…In [8], the problem of designing an IEEE P1500-compliant wrapper for hierarchical cores has been addressed. The IEEE P1500-compliant wrapper for hierarchical cores has a new set of terminals, called the CTAM terminals, which are used to access the child cores embedded in a parent core.…”

“…Test wrappers, TAMs, and test schedules designed for non-hierarchical SOCs are typically not valid for SOCs with hierarchical cores. The hierarchy imposes a number of constraints on the manner in which tests must be applied to parent cores and their embedded child cores [8]; hierarchy-oblivious methods make no attempt to satisfy these constraints.…”