We present in this paper advanced mixed signal circuits and systems techniques dedicated for wireless multichannel cortical recording devices. These design techniques enable minimum power consumption aad integration area ai buiIding blocks, which make them well suited for implantable devices including a large number of channels. Also, to address the overwhelming amount of data generated by these systems, an on-chip event detection technique is proposed for data reduction. We show that this method can increase the number of channels available in wireless implantable acquisition systems, currently limited by RF data link transfer rates. Tmdeoffs between power, area and data loss for worst case are discussed.
System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.
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