The authors propose the reuse of on-chip networks for the test of core-based systems that use this platform. Two possibilities of reuse are proposed and discussed with respect to test time minimization. An algorithm exploiting network characteristics to reduce test time is presented. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.
Networks-on-chip are likely to become the main communication platform of systems-on-chip. To cope with the growing complexity of the test of such systems, the authors propose the reuse of the on-chip network as a test access mechanism to the cores embedded into systems that use this communication platform. An algorithm exploiting the network characteristics to minimize test time is presented. Then, the reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results for the ITC'02 SOC Test Benchmarks show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized.
A new core test wrapper design approach is proposed which transports streaming test data, for example scan test patterns, into and out of an embedded core exclusively via (some of) its functional data ports. The latter are typically based on standardised protocols such as AXI, DTL, and OCP. The new wrapper design allows a functional interconnect, such as an on-chip bus or network-on-chip (NOC) to transport test data to embedded cores, and hence eliminates the need for a conventional dedicated test access mechanism (TAM), such as a TestRail or test bus. The approach leaves both the tester, as well as the embedded core and its test unchanged, while the functional interconnect can handle the test data transport as a regular data application. The functional interconnect is required to offer guaranteed throughput and zero latency variation, a service that is available in many buses and networks. For 672 example cases based on the ITC'02 System-on-Chip (SOC) Test Benchmarks, the new approach in comparison with the conventional approach shows an average wrapper area increase of 14.5%, which is negligible at the SOC level, especially since the dedicated TAM can be eliminated. Futhermore, the new approach decreases the core test length by 3.8% on average.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.