“…Finally, (11 0) tensily strained Si pMOSFETs (pseudomorphic epitaxy of Si on top of SiGe-On-Insulator substrates fabricated thanks to the Ge condensation technique) are characterized by hole mobilities superior to the one in tensily strained Si(1 0 0) [5]. The SmartCut TM industrial process can be used to fabricate (1 0 0) strained silicon-on-insulator (sSOI) substrates [2,6,7]. The very high tensile strain in the top Si layer (more than 3 GPa for Si 0.5 Ge 0.5 virtual substrates (VS) [8]) combined with a low threading dislocation density (around 10 5 cm À2 [8]) yields vastly enhanced (1 0 0) fully depleted-SOI device performances [9,10], with an increase of both electrons and holes mobilities [11,12].…”