Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling

Shin, Kyung-Ho; Choi, Woong

doi:10.1109/tcsi.2017.2691354

Cited by 43 publications

(28 citation statements)

References 21 publications

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“…However, its susceptibility to PVT variations makes reliable subthreshold operations highly challenging in the nanoscale technologies. At the same time, other design metrics such as RSNM, WSNM, and P L should be reevaluated for the reliable operation 16 . The simulation results performed at V DD = 0.3 V are given in Table 3.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…We compared the various performance metrics of the SEHF11T cell with fully differential 8T (FD8T) cell, 10 single‐ended read‐disturb‐free 9T (SEDF9T) cell, 15 and HS free bit‐sharing 9T (HFBS9T) cell 16 . The FD8T is indeed a C6T 13 and suffers from the related issues.…”

Section: Transistors Sizingmentioning

confidence: 99%

“…However, this cell occupies large area. The SRAM cells proposed in other studies 15–19 enhance the RSNM by employing read decoupling technique. However, their WSNM is still low, even lower than C6T due to the presence of two series‐connected n‐type metal–oxide–silicon (NMOS) access transistors between their bitlines and storage nodes in their write path.…”

Section: Introductionmentioning

confidence: 99%

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Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Transistors Sizingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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“…8. As is evident, the SEDF9T exhibits the longest readdelay owing to the presence of three stacked transistors in its read path, whichslows down the discharging of RBL, and the single‐ended bitline structure of thecell [31]. The BI11T cell, owing to theuse of differential‐reading scheme exhibits shorter

T_{RA}

than SEDF9T.…”

Section: Simulation Setup and Resultsmentioning

confidence: 99%

Reliable write assist low power SRAM cell for wireless sensor network applications

Pal

Bose

et al. 2020

IET Circuits, Devices & Systems

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In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Selfrefreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/ write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product (R PDP) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product (W PDP) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V DD = 0.3 V.

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“…The single ended 8T [4] and 10T [5] cells has designed for subthreshold operation to reduce or minimize energy consumption applications. The 13T model has designed to withstand for the radiation effects for the space applications [6].The 9T SRAM cell [7] avoids the half-select issues by eliminating the need to use read assistant circuit. All SRAM designs has an Q & Qb nodes to store a bit of data either '1' or'0' along with recharge and sense amplifier circuit to execute read and write operation.…”

Section: Fig 1 6 T Sram Cell Of Electric Modelmentioning

confidence: 99%

Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application.

Reddy*,

Rao,

Reddy

2020

IJRTE

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With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.

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Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling

Cited by 43 publications

References 21 publications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Reliable write assist low power SRAM cell for wireless sensor network applications

Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application.

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