Design of FinFET based 128 bit SRAM in 7nm & Various Effects near Threshold Operation for Ultra Low Power Application.

Abstract

With the existing technology and survey it indicates the increasing the number of transistors count and exploring methodologies leads to innovative design in memories. In general SRAM occupies considerable amount of area and less performance due to leakage power that limits the operation under sub threshold region. The power consumption of the circuit design is primarily depends on the switching activity of the transistor that leads to increasing of leakage current at near or subthreshold operation. Some of the challenges like PVT variations, SEU, SEE, and RDF lead to reduction in performance, increasing the power, BTI, sizing, delay and yield. The research work in this paper primarily describes the challenges with the technology and effects on CMOS & Finfet designs. The second aspect of the paper is to represents the design methodologies of CMOS & FinFET models and its operation. The third part of the paper explains design tradeoff of FinFET SRAM. Final sections present a comparison of high performance, low power at normal and near threshold operation. The Comparisons is made on the basis of process parameters and made a conclusion with circuit functionality, reliability under different technologies. FinFET based SRAM’s are the emerging memory trends by the performance under or near sub-threshold operation with the minimal variation in the leakage current, minimal gate delay is an alternate solution to the traditional CMOS memory designs as showed in the present work.

High throughput SRAM design for improved computing in autonomous systems

“…Table 3 compares the proposed design with existing FINFET and CMOS technology-based designs using various performance measures (Vasudeva Reddy et al , 2020). Here, the research obtained is the 6T of 128bit SRAM with an acceptable quantity of data existing under the PVT irregularity and aging under various FINFET devices.…”

A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor

“…Accordingly, today, electronic researchers are looking to replace dynamic random access memory (DRAM) and static random access memory (SRAM) with memory cell based on new technologies such as ferro-electronic random access memory (FeRAM), magnetic random access memory (MRAM), and resistive random access memory (RRAM) [5][6][7]. Therefore, in [8][9][10][11][12][13], cells including 3, 4, 5, 6, 7, and 8 transistors have been studied. However, all of the schemes mentioned above are volatile, meaning that power interruption can lead to the loss of information stored in these memories.…”

“…According to equation (11), the total static power can be obtained by multiplying the total leakage current and the supply voltage:…”