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This study presents a novel multilayer structure of parallel coupled‐line bandpass filtercentered at 2.42 GHz with a fractional bandwidth value of approximately 19.4%. The designed filter can suppress harmonics with an appropriate frequency response by incorporating different techniques based on the multilayer technique. A combination of different techniques such as radial microstrip stubs and defected ground structure (DGS) and defected microstrip structure techniques are employed to suppress harmonics up to 5f0. These techniques are used in two layers to suppress up to 5f0. In addition, in this study, the effects of different parameters, such as the width of slot‐line DGS, the angle of diagonal line slots in the upper layer, and the air gap between the two layers on the filter performance, are investigated. To verify the correct circuit operation, the designed filter is implemented and tested. The measurement results of the proposed filter are compared with the simulation results.

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are mostly used in the design of static cells. MOSFETs have disadvantages, such as increased leakage current, reduced reliability, increased short-channel effects, and large changes in parameters. In this paper, fin field-effect transistors (FinFETs) are used instead of MOSFETs. Memristive elements are used in the design of a nonvolatile static cell. The memory cell presented here includes a static random access memory (SRAM) core (a 6T FinFET cell in this case) with two memristors and two memcapacitors, thus making a 6T FinFET SRAM cell-based 2R2C. The designed nonvolatile memory cell performed better in terms of power consumption, energy, areal factors, static noise margin, write margin, and read/write propagation delay than other designs presented so far. The figures of merit of the proposed design are also substantially improved, making the presented scheme a better approach for 'read-write' operations. In this paper, we have tried to keep the load capacitance (C load ) as small as possible to improve the power consumption and the write and read delays, because the capacitor charge has a direct relationship with the cell's power consumption.

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