Reliable write assist low power SRAM cell for wireless sensor network applications

Abstract

In this study, the authors have proposed a Write Assist Low Power 11T (WALP11T) SRAM cell. To analyse its performance in terms of major design metrics, the proposed cell has been compared with contemporary SRAMs like the Fully Differential 8T (FD8T), Single-Ended Disturb Free 9T (SEDF9T), Bit-interleaving architecture supporting 11T (BI11T), Selfrefreshing Logic-based 12T (WWL12T) and Differential 12T (D12T) cells. The proposed cell exhibits significantly shorter read/ write delay when compared to most comparison cells. It shows considerably higher read stability and write ability than that of FD8T and SEDF9T/D12T/WWL12T, respectively. Moreover, WALP11T dissipates significantly lower leakage power in comparison to the majority of comparison cells and exhibits 2.21 × /1.18 × lower read power delay product (R PDP) than that of BI11T/D12T and 5.12 × /1.39 × /1.09 × lower write power delay product (W PDP) than that of BI11T/WWL12T/D12T. The proposed cell consumes considerably lower area than WWL12T/D12T and shows highly reliable operation when subjected to the harsh process, voltage and temperature variations at both Slow NMOS-Fast PMOS and Fast NMOS-Slow PMOS corners. For all these improvements, WALP11T shows longer read/write delay than FD8T, higher leakage power and power delay product than BI11T and FD8T/SEDF9T, respectively, at V DD = 0.3 V.

Improved read/write assist mechanism for 10‐transistor static random access memory cell

“…The simulations have been carried out using HSPICE with 16‐nm CMOS predictive technology model (PTM) 24 . Based on this technology model file, the threshold voltages ( V th ) for NMOS and PMOS are 0.47965 V and −0.43121 V, respectively, and nominal V DD is 0.7 V. To assess the relative performance of the proposed cell, its various design parameters have been compared with those of recently proposed SRAM cells such as read‐/write‐enhanced 8 T (WRE8T), 25 half‐select free bitline sharing 10T (HFBS10T), 19 differential writing 10T (10 T‐P1), 6 single‐ended 11T (SE11T), 17 and write‐assist low‐power 11T (WALP11T), 23 as shown in Figure 7. For meaningful comparisons, a 256 × 16 array has been considered to measure design metrics of the SRAM cells.…”

“…The 10T SRAM cell designed in Chien and Wang 22 removes write half-select issues, but it suffers highly from poor RSNM. The halfselection disturb-free 11T SRAM cell presented in Pal et al 23 consumes higher dynamic power and poor WSNM due to its fully differential structure and the presence of two series-connected access transistors in its write paths, respectively. This paper presents a robust low-power 10T SRAM cell (RLP10T) to overcome the aforementioned issues.…”

Radiation‐hardened read‐decoupled low‐power 12T SRAM for space applications

“…BL and BLB are precharged to reduce read access time. 18 Transistors P1, P4, P5, and N2 remain ON while P2, P3, P6, P7, P8, N1, N3, and N4 remain OFF, thereby holding the initial data. 2.…”

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

“…The major design metrics of the proposed SE12T SRAM cell compared to those of FD8T, 21 UV9T, 29 BI12T, 23 DWA12T, 24 PPN12T, 28 and PD13T 25 cells are tabulated in Table 3. In addition to these cells, two previously proposed low-power SRAM cells, namely, WALP11T 36 and P11T, 37 have been considered for a comprehensive comparison. The GNRFET-based SRAM cells show higher stability during the hold, read, and write modes.…”