GaN on sapphire mesa technology

Abstract

This contribution reports on a GaN on sapphire mesa technology for lattice matched InAlN/GaN HEMTs similar to a silicon on insulator technology. Ultrathin buffer layers between 500 nm and 100 nm have been deep mesa etched down to the substrate to avoid cross talk between devices through the buffer and provide full transparency outside the active device area (of special interest to biochemical sensor applications).The heterostructure characteristics were: NS > 1.6 x 1013 cm‐2, Rsh < 600 Ω/□. 0.25 µm gate length HEMT device characteristics are moderate, but essentially similar down to 200 nm buffer thickness. Devices on 100 nm buffer layer are still difficult to reproduce. Ion/Ioff was up to 109 and sub‐threshold slopes down to 90 mV/dec (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

GaN-on-insulator technology for high-temperature electronics beyond 400 °C

“…For RT, a previously reported off-current level of I off = 9 pA (W G = 50 μm) and a current on/off ratio larger than 10 9 were confirmed [9]. The change up to 600 • C is shown in figures 5 and 6.…”

“…The materials growth and processing technology flow have already been reported earlier [9] and may thus be only summarized shortly here. The lattice-matched InAlN/GaN material stack was grown by metal-organic chemical vapour deposition (MOCVD) on a 2 inch sapphire substrate.…”

“…Thus, as described in [9], a thin buffer layer mesa technology was developed on a sapphire substrate, which allows etching down to the insulating substrate outside the mesa and therefore enables the positioning of contacts and passive components directly onto the insulator. Compared to 0268-1242/13/074026+05$33.00 conventional (shallow mesa etching, thick buffer) technology, this ultrathin body SOI-like technology resulted in very low leakage levels and current on/off ratios as high as 10 9 . In this paper, we describe a similar ultrathin body SOI-like technology designed for high-temperature electronics, i.e.…”

Analysis of current instabilities of thin AlN/GaN/AlN double heterostructure high electron mobility transistors

“…A particularly interesting case of AlN/GaN/AlN double heterostructures are those consisting of a very thin GaN channel/buffer layer and a very thin AlN buffer/nucleation layer on an insulating substrate, such as sapphire (Al 2 O 3 ) [21]. The small total thickness of the heteroepitaxial structure allows one to form mesas down to the insulating substrate, which is the optimum configuration to reduce leakage currents and cross-talk between devices [24]. The reduction of the GaN buffer/channel layer thickness from 500 nm to 200 nm has also been found [24] to reduce the off-state leakage current of InAlN/GaN HEMT devices from 1.2×10 −9 A mm −1 to 1.8×10 −10 A mm −1 , respectively.…”

“…The small total thickness of the heteroepitaxial structure allows one to form mesas down to the insulating substrate, which is the optimum configuration to reduce leakage currents and cross-talk between devices [24]. The reduction of the GaN buffer/channel layer thickness from 500 nm to 200 nm has also been found [24] to reduce the off-state leakage current of InAlN/GaN HEMT devices from 1.2×10 −9 A mm −1 to 1.8×10 −10 A mm −1 , respectively. The thin heteroepitaxial layers will contain a higher density of dislocations compared to a thicker buffer layer.…”