Finite state machine decomposition for low power

Monteiro, José; Oliveira, Arlindo L.

doi:10.1145/277044.277235

Cited by 68 publications

(24 citation statements)

References 17 publications

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“…For state partitioning, we use Kernighan-Lin algorithm to find a small cluster of states composing the first sub-FSM and all other states composing the second one [9]. The cost function is based on transition probability and the smaller sub-FSM should has high probability of state transitions inside itself, and low probability of crossing transitions to the other sub-FSM.…”

Section: Resultsmentioning

confidence: 99%

Mixed synchronous/asynchronous state memory for low power FSM design

Cao

Oelmann

2004

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

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Finite state machine (FSM) partitioning proves effective for power optimization. In this paper we propose a design model based on mixed synchronous/asynchronous state memory that results in implementations with low power dissipation and low area overhead for partitioned FSMs. The state memory here is composed of the synchronous local state memory and asynchronous global state memory, where the former is used to distinguish the states inside a sub-FSM, and the latter is responsible for controlling sub-FSM communication. The input and output behaviour of the decomposed FSM is cycle by cycle equivalent to the undecomposed synchronous FSM. Together with clock gating technique, substantial power reduction can be demonstrated.

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Section: Resultsmentioning

confidence: 99%

Mixed synchronous/asynchronous state memory for low power FSM design

Cao

Oelmann

2004

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

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“…Decomposition of finite state machines for low power has been proposed in [21]. The basic idea is to decompose the STG of a finite state machine (FSM) into two STGs that jointly produce the equivalent input-output behavior as the original machine.…”

Section: State Machine Decompositionmentioning

confidence: 99%

Low-power RT-level synthesis techniques: a tutorial

Pedram

Abdollahi

2005

IEE Proc., Comput. Digit. Tech.

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-Power consumption and power-related issues have become a first-order concern for most designs and loom as fundamental barriers for many others. And, while the primary method used to date for reducing power has been supply voltage reduction, this technique begins to lose its effectiveness as voltages drop to sub-one volt range and further reductions in the supply voltage begin to create more problems than are solved. Under these circumstances, the process of design and the automation tools required to support that process become the critical success factors. In the last decade, huge effort has been invested to come up with a wide range of design solutions that help solve the power dissipation problem for different types of electronic devices, components and systems. These techniques range from RTL power management and multiple voltage assignment, to power-aware logic synthesis and physical design, to memory and bus interface design. This tutorial paper explains a number of representative low power design techniques from this large set. More precisely, we will describe basic techniques, applicable at RT-level and below, that have proven to hold good potential for power optimization in practical design environments.

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“…Other techniques for reducing switching activities, including loop folding [8] and finite state machine decomposition [14], have also been studied. In addition, the effect of high-level compiler optimizations on system power has been investigated [7].…”

Section: Preliminariesmentioning

confidence: 99%

The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

Wilton

Ang

Luk

2004

Field Programmable Logic and Application

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Abstract. This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18µm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.

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Finite state machine decomposition for low power

Cited by 68 publications

References 17 publications

Mixed synchronous/asynchronous state memory for low power FSM design

Mixed synchronous/asynchronous state memory for low power FSM design

Low-power RT-level synthesis techniques: a tutorial

The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

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