This paper describes an analytical model for the access and cycle times of on-chip directmapped and set-associative caches. The inputs to the model are the cache size, block size, and associativity, a s w ell as array organization and process parameters. The model gives estimates that are within 6 of Hspice results for the circuits we h a ve c hosen. This model extends previous models and xes many of their major shortcomings. New features include models for the tag array, comparator, and multiplexor drivers, non-step stage input slopes, rectangular stacking of memory subarrays, a transistor-level decoder model, column-multiplexed bitlines controlled by an additional array organizational parameter, load-dependent size transistors for wordline drivers, and output of cycle times as well as access times. Software implementing the model is available via ftp.

Abstract. This paper describes a flexible power model for FPGAs. The model estimates the dynamic, short circuit, and leakage power for a wide variety of FPGA architectures. Such a model will be essential in the design and research of next-generation FPGAs, where power will be one of the primary optimization goals. The model has been integrated into the VPR CAD flow, and is available to the research community for use in FPGA architectural and CAD tool experimentation.

________________________________________________________________________Power has become a critical issue for FPGA vendors. Understanding the power dissipation within FPGAs is the first step to develop power-efficient architectures and CAD tools for FPGAs. This paper describes a detailed and flexible power model which has been integrated in the widely-used Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, short-circuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of power-aware CAD tools for a variety of FPGA architectures, and is freely available for non-commercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookup-table size, and cluster size.

No abstract

Reconfigurable computing is becoming increasingly attractive for many applications. This survey covers two aspects of reconfigurable computing: architectures and design methods. The paper includes recent advances in reconfigurable architectures, such as the Alters Stratix II and Xilinx Virtex 4 FPGA devices. The authors identify major trends in general-purpose and specialpurpose design methods. It is shown that reconfigurable computing designs are capable of achieving up to 500 times speedup and 70% energy savings over microprocessor implementations for specific applications.