Reconfigurable computing: architectures and design methods

Todman, Tim; Constantinides, George A.; Wilton, Steven J. E.; Mencer, Oskar; Luk, Wayne; Cheung, Peter Y. K.

doi:10.1049/ip-cdt:20045086

Cited by 275 publications

(74 citation statements)

References 82 publications

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“…[5] presented a practical parallel computation models named the LogGP synchronization model, which is based on non-exclusive heterogeneous and reflected the impact of heterogeneity and non-exclusive computing environment for concurrent algorithm design and analysis from the system level. A reconfigurable architecture [6] was analyzed and gave the design method for general purpose and special purpose in energy consumption level multi-processor in special applications with 500 times performance improvement, and 70% energy saving. [7] pointed out that a reconfigurable architecture can make the hardware resources behavior to adapt to the special computing requirements on hardware resources level, which provides an interactive mechanism to maximize the use of logic resources.…”

Section: Related Workmentioning

confidence: 99%

A Reconfigurable Architecture via Grain Perception Operator

Yang¹,

Shen²,

Li³

et al. 2016

Proceedings of the 2016 International Conference on Intelligent Control and Computer Application

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Abstract-Application tasks are complex and diverse, which need HPC (High Performance Computing) to solve them. The computing efficiency is hugely different when they run in different architectures, because different application tasks have different computing features. The PMC (Processor-MemoryCommunication) resource requirements of application tasks are perceived to get PMC operating grain, and the best matched architecture is assigned to the application. Hypergraph is used to describe the application structure and the computing architecture, and its isomorphic principle is utilized to build and demonstrate the super-mixed heterogeneous architecture. Experiments show that reconfigurable architecture based on operator grain perception has characteristic high computing and low energy consumption.

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Section: Related Workmentioning

confidence: 99%

A Reconfigurable Architecture via Grain Perception Operator

Yang¹,

Shen²,

Li³

et al. 2016

Proceedings of the 2016 International Conference on Intelligent Control and Computer Application

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“…Fine grained structure means functions defined using single or number of bits, such as look up table for implementing logic. Fig.4a [3] shows implementing of three inputs single function, cluster of LUT is shown in Fig.4b [3]. Fig.5 shows logic block architecture of virtex5 which has six inputs LUT [4].…”

Section: Reconfigurable Functional Unitsmentioning

confidence: 99%

An Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms

Kadam¹

2014

IOSRJEN

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-Reconfigurable hardware is emerging as the best option for the efficient implementation of complex and computationally expensive signal processing algorithms. Reconfigurable hardware exploits the benefit of high of computational efficiency of hardware as well as flexibility of software implementation. Field Programmable Gate Array (FPGA) which finds wide range of applications in the field of signal processing, wireless communication, image and video processing has gained popularity as a reconfigurable logic over past decade. In this paper, various hardware aspects of reconfigurable such as architectures and models including external coupling and run-time reconfigurable systems have been studied. Moreover, a case study of most widely used commercial FPGA technologies from Xilinx and upcoming three dimensional 3D-FPGA architecture is presented. It is revealed that the reconfigurable hardware can be used in a variety of DSP applications. FPGA implementation of digital signal processing applications show enhanced outcome in terms of speed as compared to software implementation and previously reported architecture.

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“…Many authors consider task scheduling and prefetching techniques to hide reconfiguration time from the application [4,5,2,8,6]. However, reduced configuration data and power can be achieved by the use of custom reconfigurable architectures [3,14] or by advanced implementation methods that exploit similar properties of tasks. In [9] a method that uses remapping of LUT based logic in FPGAs is proposed.…”

Section: Introductionmentioning

confidence: 99%

Maximum edge matching for reconfigurable computing

Rullmann

Merker

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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Reconfiguration of tasks implies considerable overhead on the amount of configuration data and time. Much overhead is caused by redundant configuration generated by the design tools which implement similar structures in the designs on different resources. In this paper we propose a new method to identify structural similarities in tasks. Based on this information, we are able to generate automatically constraints to ensure that the place and route tools use identical resources. Thus we ensure that less redundant configuration is produced. In this paper we give a formal description of the underlaying maximum edge matching problem and show a method to solve it optimally. We derive a truncation criteria to restrict the search space efficiently. We also propose an Ant Colony Optimization based solution with a problem specific local heuristic and show that it performs optimal as well in our examples, but with considerable lower computational effort.

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Reconfigurable computing: architectures and design methods

Cited by 275 publications

References 82 publications

A Reconfigurable Architecture via Grain Perception Operator

A Reconfigurable Architecture via Grain Perception Operator

An Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms

Maximum edge matching for reconfigurable computing

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