Low-power RT-level synthesis techniques: a tutorial

Abstract

-Power consumption and power-related issues have become a first-order concern for most designs and loom as fundamental barriers for many others. And, while the primary method used to date for reducing power has been supply voltage reduction, this technique begins to lose its effectiveness as voltages drop to sub-one volt range and further reductions in the supply voltage begin to create more problems than are solved. Under these circumstances, the process of design and the automation tools required to support that process become the critical success factors. In the last decade, huge effort has been invested to come up with a wide range of design solutions that help solve the power dissipation problem for different types of electronic devices, components and systems. These techniques range from RTL power management and multiple voltage assignment, to power-aware logic synthesis and physical design, to memory and bus interface design. This tutorial paper explains a number of representative low power design techniques from this large set. More precisely, we will describe basic techniques, applicable at RT-level and below, that have proven to hold good potential for power optimization in practical design environments.

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC

“…Although this structure is highly regular, it is also power inefficient since all the DFFs are activated every clock cycle. In order to save power, we propose a design of the transpose register based on the clock-gating technique [25,26] where only one row or column of registers out of 8 is selected while the other registers are inactive. As a result, this scheme reduces the power dissipation to one-eighth in the ideal case.…”

Automatic Register Transfer level CAD tool design for advanced clock gating and low power schemes

“…Considering Moore's Law and the trend of industrial technology, integrated circuit densities and operating speeds have continued to go up during the past decades of years, and this change will be unabated [5]. With this rapid progress of technology, there will be larger chips, more complex design, faster operation time and then result in tremendously increased power consuming.…”

“…For Register-transfer level, digital circuits always contain some computations which are redundant, in other words, power reduction can be achieved by reducing these idle circuit operations [5]. Clock gating (CG) is the most widely used and effective technique at RTL.…”

Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design

“…Clock gating (CG) is the most popular, widely used and effective technique at RTL. For Register transfer level, digital circuits always contain some computations which are redundant, in other words, power reduction can be achieved by switching off these idle circuit operations [8].…”