Background and objectivesVital signs are usually recorded at 4–8 h intervals in hospital patients, and deterioration between measurements can have serious consequences. The primary study objective was to assess agreement between a new ultra-low power, wireless and wearable surveillance system for continuous ambulatory monitoring of vital signs and a widely used clinical vital signs monitor. The secondary objective was to examine the system's ability to automatically identify and reject invalid physiological data.SettingSingle hospital centre.ParticipantsHeart and respiratory rate were recorded over 2 h in 20 patients undergoing elective surgery and a second group of 41 patients with comorbid conditions, in the general ward.Outcome measuresPrimary outcome measures were limits of agreement and bias. The secondary outcome measure was proportion of data rejected.ResultsThe digital patch provided reliable heart rate values in the majority of patients (about 80%) with normal sinus rhythm, and in the presence of abnormal ECG recordings (excluding aperiodic arrhythmias such as atrial fibrillation). The mean difference between systems was less than ±1 bpm in all patient groups studied. Although respiratory data were more frequently rejected as invalid because of the high sensitivity of impedance pneumography to motion artefacts, valid rates were reported for 50% of recordings with a mean difference of less than ±1 brpm compared with the bedside monitor. Correlation between systems was statistically significant (p<0.0001) for heart and respiratory rate, apart from respiratory rate in patients with atrial fibrillation (p=0.02).ConclusionsOverall agreement between digital patch and clinical monitor was satisfactory, as was the efficacy of the system for automatic rejection of invalid data. Wireless monitoring technologies, such as the one tested, may offer clinical value when implemented as part of wider hospital systems that integrate and support existing clinical protocols and workflows.

Abstract. This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPGA (Altera Stratix EP1S40), and a 0.18µm CMOS low-cost FPGA (Xilinx XC2S200). The results are obtained by both measurements and execution of vendor-supplied tools for power estimation. It is found that pipelining can reduce the amount of energy per operation by between 40% and 90%. Further reduction in energy consumption can be achieved by power-aware clustering, although the effect becomes less pronounced for circuits with a large number of pipeline stages.

This paper presents SensiumVitals(®) - an FDA cleared and CE marked wireless wearable vital signs monitoring system, developed for frequent surveillance of in-hospital patients. A number of in-house evaluations with artificial data and healthy volunteers were carried out in different stages to assess the reliability of two crucial vital signs measured by the system - respiration and heart rate. In order to illustrate the potential of the system in hospital, a subset of data collected from acutely-ill patients during a separate clinical trial was also analyzed. In all cases the results revealed satisfactory agreement between the values reported by SensiumVitals(®) and those recorded simultaneously by a clinically-approved bedside monitor. However, further work will be required to improve the reliability of the system under certain clinical conditions; which, although not crucial for our intended population (i.e. patients in general ward), pose interesting challenges for upgrading our technology for future use in these types of patients.

Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much work has been done on the exploitation of data re-use for algorithms that exhibit static memory access patterns in FPGAs. The proposed scheme enables the exploitation of data re-use for both static and non-static parallel memory access patterns through the use of a multi-port cache, where parameters can be determined at compile time and matched to the statistical properties of the application, and where sub-cache contentions are arbitrated with a semaphore-based system. A complete hardware implementation demonstrates that, for a motion vector estimation benchmark, the proposed caching scheme results in a cycle count reduction of 51% and execution time reduction of up to 24%, using a Xilinx XC2V6000 FPGA on a Celoxica RC300 board. Hardware resource usage and clock frequency penalties are analyzed while varying the number of ports and cache size. Consequently, it is demonstrated how the optimum cache size and number of ports may be established for a given datapath.

In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Field Programmable Gate Arrays (FPGAs) is becoming increasingly desirable, because of the computational parallelism on these platforms as well as the measure of flexibility afforded to designers. Typically, video data is stored in large and slow external memory arrays, but the impact of the memory access bottleneck may be reduced by buffering frequently used data in fast on-chip memories. The order of the memory accesses, resulting from many compression algorithms are dependent on the input data [18]. These data dependent memory accesses complicate the exploitation of data re-use, and subsequently reduce the extent to which an application may be accelerated. In this paper, we present a hybrid memory sub-system which is able to capture data re-use effectively in spite of data dependent memory accesses. This memory sub-system is made up of a custom parallel cache and a scratchpad memory. Further, the framework is capable of exploiting two dimensional spatial locality, which is frequently exhibited in the access patterns of image processing applications. In a case study involving the Quad-tree Structured Pulse Code Modulation (QSDPCM) application, the impact of data dependence on memory accesses is shown to be significant. In comparison with an implementation which only employs an SPM, performance improvements of up to 1.7× and 1.4× are observed through actual implementation on two modern FPGA platforms. These performance improvements are more pronounced for image sequences exhibiting greater inter-frame movements. In addition, reductions of on-chip memory resources by up to 3.2× are achievable using this framework. These results indicate that, on custom hardware platforms,

Abstract-Motion vector estimation is frequently performed as a prelude to the exploitation of temporal redundancies in video applications. As a result, a large volume of work has been done to develop techniques to avoid the heavy memory access requirements of full search motion vector estimation. Often, these approaches introduce data dependence to the algorithm, leading to memory accesses which cannot be determined at design time. Consequently, this complicates the exploitation of data reuse in hardware. In this work, the cost of data dependence is quantified. Experiments indicate that a data dependent fast motion vector estimation approach is faster than full search by up to 47% in the absence of data re-use optimisation. However, full search is approximately 16 times faster than the 'fast' motion vector estimation algorithm when a static line buffering scheme and a parallel caching scheme are used respectively to exploit data re-use. Therefore, it is established that data dependence in motion vector estimation is very expensive in terms of hardware performance.

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