A Flexible Multi-port Caching Scheme for Reconfigurable Platforms

Ang, Su-Shin; Constantinides, George A.; Cheung, Peter Y. K.; Luk, Wayne

doi:10.1007/11802839_29

Cited by 9 publications

(8 citation statements)

References 12 publications

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“…for applications with memory parallelism. Ang et al likewise describes a multi-ported cache, where independent sub-caches correspond to separate partitions of the global address space [6]. The techniques described in our paper, however, are independent of the accelerator memory access patterns and thus are orthogonal to the memory partitioning approach.…”

Section: A Memory Architecture In Fpga-based Computingmentioning

confidence: 99%

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Choi

Nam

Canis

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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Abstract-We describe new multi-ported cache designs suitable for use in FPGA-based processor/parallel-accelerator systems, and evaluate their impact on application performance and area. The baseline system comprises a MIPS soft processor and custom hardware accelerators with a shared memory architecture: on-FPGA L1 cache backed by off-chip DDR2 SDRAM. Within this general system model, we evaluate traditional cache design parameters (cache size, line size, associativity). In the parallel accelerator context, we examine the impact of the cache design and its interface. Specifically, we look at how the number of cache ports affects performance when multiple hardware accelerators operate (and access memory) in parallel, and evaluate two different hardware implementations of multi-ported caches using: 1) multi-pumping, and 2) a recently-published approach based on the concept of a livevalue table. Results show that application performance depends strongly on the cache interface and architecture: for a system with 6 accelerators, depending on the cache design, speedup swings from 0.73× to 6.14×, on average, relative to a baseline sequential system (with a single accelerator and a direct-mapped, 2KB cache with 32B lines). Considering both performance and area, the best architecture is found to be a 4-port multi-pump direct-mapped cache with a 16KB cache size and a 128B line size.

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Section: A Memory Architecture In Fpga-based Computingmentioning

confidence: 99%

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Choi

Nam

Canis

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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“…Unfortunately, multi-port memories require larger area, provide slower access time, and higher power consumption than single-port memories. Recently multi-port memories have been considered in field-programmable gate array designs, e.g., in [1,2], but there the memories are predefined modules with additional logic. Therefore, the cost of memory organization is different than in other gate array technologies where the basic building block is gate.…”

Section: Related Workmentioning

confidence: 99%

Parallel Memory Architecture for Application-Specific Instruction-Set Processors

Pitkänen

Tanskanen

Makinen³

et al. 2008

J Sign Process Syst Sign Image Video Technol

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Many of the current applications used in battery powered devices are from digital signal processing, telecommunication, and multimedia domains. These applications typically set high requirements for computational performance and often parallelism is the key solution to meet the performance requirements. In order to exploit the parallel processing units, memory should be able to feed the data path with data. This calls for a memory organization supporting parallel memory accesses. In this paper, a conflict resolving parallel data memory system for application-specific instruction-set processors is described. The memory structure is generic and reusable to support various application-specific designs. The proposed memory system does not employ any predefined access format signals for memory addressing. The proposed parallel memory system is attached to an application-specific instruction-set processor core and comparison on area, power, and critical path are shown. The experiments show that significant power savings can be obtained by exploiting the parallel memory system instead of multiport memory.

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“…A caching approach [8], which can cope with dynamic memory accesses and exploit hardware parallelism is used with the data dependent algorithm. Full search is optimised with a scratchpad memory (SPM).…”

Section: Introductionmentioning

confidence: 99%

The cost of data dependence in motion vector estimation for reconfigurable platforms

Ang¹,

Constantinides²,

Luk³

et al. 2006

2006 IEEE International Conference on Field Programmable Technology

Self Cite

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Abstract-Motion vector estimation is frequently performed as a prelude to the exploitation of temporal redundancies in video applications. As a result, a large volume of work has been done to develop techniques to avoid the heavy memory access requirements of full search motion vector estimation. Often, these approaches introduce data dependence to the algorithm, leading to memory accesses which cannot be determined at design time. Consequently, this complicates the exploitation of data reuse in hardware. In this work, the cost of data dependence is quantified. Experiments indicate that a data dependent fast motion vector estimation approach is faster than full search by up to 47% in the absence of data re-use optimisation. However, full search is approximately 16 times faster than the 'fast' motion vector estimation algorithm when a static line buffering scheme and a parallel caching scheme are used respectively to exploit data re-use. Therefore, it is established that data dependence in motion vector estimation is very expensive in terms of hardware performance.

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A Flexible Multi-port Caching Scheme for Reconfigurable Platforms

Cited by 9 publications

References 12 publications

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems

Parallel Memory Architecture for Application-Specific Instruction-Set Processors

The cost of data dependence in motion vector estimation for reconfigurable platforms

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