Mixed synchronous/asynchronous state memory for low power FSM design

Abstract

Finite state machine (FSM) partitioning proves effective for power optimization. In this paper we propose a design model based on mixed synchronous/asynchronous state memory that results in implementations with low power dissipation and low area overhead for partitioned FSMs. The state memory here is composed of the synchronous local state memory and asynchronous global state memory, where the former is used to distinguish the states inside a sub-FSM, and the latter is responsible for controlling sub-FSM communication. The input and output behaviour of the decomposed FSM is cycle by cycle equivalent to the undecomposed synchronous FSM. Together with clock gating technique, substantial power reduction can be demonstrated.

A Uniform Framework of Low Power FSM Partition Approach

“…From Table 2, it can be seen that the average power reduction is 21.7% with 62% area trade-off while the power reduction from the model in [7] is 20.8% with the significant area trade-off up to 131.4% compared with the results of monolithic FSM implementation. It can be concluded that the proposed model has better performance in terms of power dissipation and area than the model in [7].…”

“…It can be concluded that the proposed model has better performance in terms of power dissipation and area than the model in [7].…”

“…The results for next four columns are from the proposed design model. For the comparison among the proposed model and other published models, the next eight columns list the results from the monolithic FSMs and the model published in [7]. The power and area reduction are defined based on the results from monolithic FSMs as follows.…”

“…The main difference between the proposed model and that in [7] is that the proposed model does not employ clock-gating techniques, which simplifies the circuit and the state assignment as well. And also the proposed model implements the transition between sub-FSMs synchronously.…”

“…S4 and s6 in MI are the mirror states of s4 and s6 from M2; S5 in M2 is the mirror state of s5 from MI. The proposed design model is inspired from the model in [7]. The structure is shown in Fig.…”