A Uniform Framework of Low Power FSM Partition Approach

Abstract

A new Finite State Machine (FSM) partitioning approach is proposed in this paper. Genetic Algorithm (GA) is employed to search the optimal or near optimal partition. A new cost function is used to guide the optimization. The proposed algorithm is implemented in C. A new design model is proposed to implement partitioned sub-FSMs, which makes the existing monolithic FSM state assignment be applicable to partitioned FSMs. The experiment results show that the proposed approach can reduce power dissipation up to 80%.

MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis

“…For low‐power FSM synthesis, many researchers used decomposition or partition technique to accomplish the task [6, 7, 31, 32]. Choudhury et al .…”

“…However, it mainly focused on only dynamic power reduction; Xia et al proposed another low‐power FSM partition method. By using partition of FSMs, the switching power dissipation can be reduced up to 80% [7]. Reddy et al presented a partitioning‐based state encoding approach target to low power [8]; Pradhan et al proposed a high‐performance method to trade fault coverage with power for FSM synthesis [33]; Klimowicz et al used minimisation method of FSM for low‐power design, which takes possibility of merging other states into account at the stage of minimising internal states [34].…”

“…Previous works mainly focused on dynamic power minimisation of FSM. State encoding [3–5] and power management [6–8] are two efficient alternatives for the power reduction at gate‐level synthesis. Power management saves the total power by shutting off the blocks of hardware when they are not active (i.e.…”

State assignment for sequential circuits using multi-objective genetic algorithm

“…The proposed heuristic is based on a branch-and-bound search technique and identification of sets of compatible states of a given ISFSM specification. A new FSM partitioning approach for low power using GA is presented in [12].…”

“…Generally, it is possible to find state assignments to minimise the hardware only [1][2][3]15], or the power dissipation only [4,12,16,17]. It is known, however, that minimising either the power or logic complexity could be at the expense of the other and in most cases it is not possible to find a solution that is optimum in both domains.…”