Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory

Cao, Cao; Oelmann, Bengt

doi:10.1016/j.vlsi.2007.02.002

Cited by 4 publications

(6 citation statements)

References 6 publications

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“…Gated clock has been employed normally to selectively stop the clock in portions of circuits where active computation is not being performed [12]. In [12], the Finite State Machine (FSM) is partitioned into several sub-FSMs and these sub-FSMs are clocked when necessary.…”

Section: Low Power Clocking Schemementioning

confidence: 99%

“…In [12], the Finite State Machine (FSM) is partitioned into several sub-FSMs and these sub-FSMs are clocked when necessary. In this paper, an AMBA-based low power clocking scheme is devised for the interface to reduce the switching activity in the AMBA interface and the connecting DSP IP Cores.…”

Section: Low Power Clocking Schemementioning

confidence: 99%

“…The DSP IP cores used in this paper are based on an FIR filter with similar architectures [11] [12]. These are all based on a transpose direct form structure which reduces the switching activity at data inputs of the multiplier.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

Shrivastavastava¹,

Tomar²,

Kalra

2010

2010 International Conference on Computational Intelligence and Communication Networks

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This paper describes a System-on-Chip platform architecture for low power high performance Digital Signal Processing intensive applications. The platform is based on the AMBA SoC bus protocol and incorporates a novel interfacing scheme which utilizes the bus hierarchy within AMBA in order to allow single and multiple high performance DSP Intellectual Property cores to be integrated to the SoC platform. The paper describes the overall SoC platform architecture and the integration scheme, providing results for area usage and power consumption of the main blocks in the platform with an example of a three DSP core integration case.

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Section: Low Power Clocking Schemementioning

confidence: 99%

Section: Low Power Clocking Schemementioning

confidence: 99%

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Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

Shrivastavastava¹,

Tomar²,

Kalra

2010

2010 International Conference on Computational Intelligence and Communication Networks

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“…RELATED WORK Different algorithms have been proposed to select the states of each sub-FSM, such as genetic algorithm [13] and KernighanLin algorithm [14]. All depart of original STG added with probabilistic information, as transition probability and state probability [13]. We can classify two types of target architecture: power-gated [15] and gated-clock [4].…”

Section: Introductionmentioning

confidence: 99%

“…For each state transition of STG, find the probabilities of transition and of state using the algorithm in [13]. Generate the STG*.…”

mentioning

confidence: 99%

Asynchronous burst-mode control for low-power gated-clock finite state machines

Oliveira

Ferreira

2011

2011 IEEE Second Latin American Symposium on Circuits and Systems (LASCAS)

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Design of contemporary digital circuits has great need of power reduction. The reasons are owing to portable applications and CMOS Deep-Sub-Micron technology. Finite state machines (FSM) play an important role in these circuits. The partitioning of an FSM into several sub-FSMs is a technique widely used in the reduction of energy consumption. An interesting style for activating and deactivating sub-FSMs is the asynchronous communication proposed by Oelmann. In this paper we propose a high performance control to the asynchronous communication between sub-FSMs. Compared with Oelmann's control, our control consumes less power, occupies less area and has a smaller cycle time.

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