Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

Shrivastavastava, Anurag; Tomar, Geetam Singh; Kalra, Kamal K.

doi:10.1109/cicn.2010.129

Cited by 6 publications

(3 citation statements)

References 10 publications

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“…We build a multi-core system with ABMA to verify the design [9] . In this system ARM9 is the main processor mounted on AHB and MV10 on APB [10] . MV10 acts as a low-power and low-speed slaver.…”

Section: Verification Environment and Simulation Resultsmentioning

confidence: 99%

Implementation of advanced peripheral bus interface for MV10 MCU

Huang

Zhou

2011

J. Shanghai Univ.(Engl. Ed.)

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MV10 is an MCU which consists of PWM, ADC,CAN and some other function blocks. It is designed for car body's control. Advanced peripheral bus (APB) is a low speed AMBA bus connecting low-power peripherals. This paper presents an implementation of APB interface for MV10 MCU. After that, MV10 can be integrated into any AMBA system on chips (SoCs) easily. We have built a multi-core system with ABMA to verify this design. In this system ARM9 is a main processor mounted on AHB and MV10 acts as a low-power and low-speed slaver on APB. Before building this system, some operations are encapsulated into a task with dedicated ID. MV10 works as a co-processor with ARM by acquiring task ID from ARM. The result of simulation indicates that MCU can work well as expected. Based on our design, MV10 can be mounted on any AMBA system from now on.

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Section: Verification Environment and Simulation Resultsmentioning

confidence: 99%

Implementation of advanced peripheral bus interface for MV10 MCU

Huang

Zhou

2011

J. Shanghai Univ.(Engl. Ed.)

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“…The three thermal possessions are related to FPGA which are termed such as Under operating conditions, it is expressed the temperature around the FPGA [21][22][23] (iii) Junction temperature (JT) ( °C). It is called as the operational temperature of the FPGA [5,24].…”

Section: Thermal Properties For Different Voltage Valuesmentioning

confidence: 99%

Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector

Haripriya

Kumar

Shrivastava³

et al. 2022

Wireless Communications and Mobile Computing

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In the present scheme of the world, the problem of shortage of power is seen across the world which can be a vulnerability to various communication securities. The scope of proposed research is that it is a step towards completing green communication technology concepts. In order to improve energy efficiency in communication networks, we designed UART using different nanometers of FPGA, which consumes the least amount of energy. This shortage is happening because of expanding of industries across the world and the rapid growth of the population. Therefore, to save the power for our upcoming generation, the globe is moving towards the concept and ideas of green communication and power-/energy-efficient gadget. In this work, a power-efficient universal asynchronous receiver transmitter (UART) is implemented on 28 nm Artix-7 field-programmable gate array (FPGA). The objective of this work is to reduce the power utilization of UART with the FPGA device in industries. To do this, the same authors have used voltage scaling techniques and compared the results with the existing FPGA works.

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“…Wei and Cheng [11] called the partitioning problem as Rcut, which uses FM heuristic followed by left and right shift to be able to find small cut partitions. Apart from these, some other approaches were also tried, such as clustering [12,13] and spectral [14] algorithms, neural network algorithm [15], simulated annealing algorithms [16] using graph based approach. Wang [17] have used Ant Colony Optimization (ACO) technique for circuit partitioning.…”

Section: Existing Partitioning Techniquesmentioning

confidence: 99%

An Efficient Approach to VLSI Circuit Partitioning Using Evolutionary Algorithms

Sangwan

Verma

Kumar

2014

2014 International Conference on Computational Intelligence and Communication Networks

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Circuit Partitioning generally formulated as graph partitioning problem is an important step in physical design of circuits. The use of Evolutionary techniques is increasingly used to solve NP complete problems i.e. applications for logic minimization and simulation heuristics. This paper explores the evolutionary approach of genetic algorithm and propose a hybrid technique involving the strengths of the existing techniques resulting in a better partitioning and placement of circuits. It can further be extended to the Hardware/Software boundary of algorithms and can be applied to real world physical design problems.

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Efficient Design and Performance Analysis for AMBA Bus Architecture Based System-on-Chip

Cited by 6 publications

References 10 publications

Implementation of advanced peripheral bus interface for MV10 MCU

Implementation of advanced peripheral bus interface for MV10 MCU

Energy-Efficient UART Design on FPGA Using Dynamic Voltage Scaling for Green Communication in Industrial Sector

An Efficient Approach to VLSI Circuit Partitioning Using Evolutionary Algorithms

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