Fast, layout-inclusive analog circuit synthesis using pre-compiled parasitic-aware symbolic performance models

Ranjan, Madhu; Verhaegen, Wim; Agarwal, Anuradha M.; Sampath, H.; Vemuri, Ranga; Gielen, Georges

doi:10.1109/date.2004.1268911

Cited by 39 publications

(25 citation statements)

References 16 publications

(14 reference statements)

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“…Vancorenland et al [32] used manually derived equations along with a procedural layout generation approach to find a suitable solution. Ranjan et al [33] generates a parameterized layout using the module specification language system, which consists on a fixed template layout, and when the circuit parameters are provided it produces a physical layout. Then, the extracted parasitic from the layout, along with the passive component values are passed to the precompiled symbolic performance models (symbolic equations in terms of circuit parameters), which predicts the circuit performance at each iteration avoiding numerical simulations.…”

Section: Layout-aware Sizing Approachesmentioning

confidence: 99%

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State of the Art on Analog Layout Automation

Martins¹,

Lourenço²,

Horta³

2012

Generating Analog IC Layouts With LAYGEN II

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In the past few years, several tools for the automation of the analog integrated circuit (IC) cell and system layout design, with application on both new and reused designs have emerged. Yet, most of the layout design is still handmade, essentially because analog designers want to have total control over the different design options, and also, due to the fact that current fully automated generators of analog IC layouts produce solutions which are not yet competitive with the manually crafted ones. The state-of-the-art on analog layout automation that follows reveals that after many years of stagnation, electronic design automation (EDA) market is evolving, creating more efficient and complementary approaches to the existing tools. The chapter starts by addressing the placement problem in EDA, providing a brief overview of the most recent placement tools developed, followed by the presentation of the main references of automatic layout generation tools, and the recent advances in layout-aware analog synthesis approaches. Finally, the available commercial solutions for analog layout automation are outlined.

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Section: Layout-aware Sizing Approachesmentioning

confidence: 99%

“…Ranjan [33] ALDAC [30] KOAN/ANAGRAM [27] ALADIN [23] LAYLA [28] Castro-Lopez [31] Zhang [25] Malavasi [29] Koda [16] Lin [18] ALG [24] Habal [35] Jingnan [20] Vancorenland [32] ALSYN [19] Legend:…”

Section: Template Optimizationmentioning

confidence: 99%

State of the Art on Analog Layout Automation

Martins¹,

Lourenço²,

Horta³

2012

Generating Analog IC Layouts With LAYGEN II

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“…As shown in [6] and [7], this mechanical stress is highly dependent on the layout style being used. To reduce the impact of mechanical stress, the layout must be designed so that all the transistors of the device are affected in the same way.…”

Section: ) the Shallow Trench Isolation (Sti)mentioning

confidence: 99%

“…In the following, we discuss the stress effects calculations for the layout styles: mirror and interdigitation. The stress effect parameters for differential pair can be calculated as the transistor device by treating each transistor (T1 and T2) separately using the equations (3)- (6).…”

Section: Stress Effect Parameter Computation 1) the Stress Effectsmentioning

confidence: 99%

A Python-based layout-aware analog design methodology for nanometric technologies

Youssef

Javid

Dupuis

et al. 2011

2011 IEEE 6th International Design and Test Workshop (IDT)

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Abstract-This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python API that ensures layout portability over different technologies. A main focus is on how the layout generation tool addresses both geometric and parasiticaware electrical synthesis. This is made possible through an internal loop that links circularly both the sizing phase and the layout generation phase. The proposed design methodology assists the analog designer in exploring electrical and physical trade-offs. At the end, we present synthesis and characterization results that prove the effectiveness and speed of the proposed methodology.

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“…Also, one or more description levels may be included in the synthesis techniques. For example, layout-aware approaches operate on both circuit and physical level when determining the dimensions of the transistors [3,4].…”

Section: Introductionmentioning

confidence: 99%