We present a new methodology for fast analog circuit synthesis, based on the use of parameterized layout generators and symbolic performance models (SPMs) in the synthesis loop. Fast layout generation is achieved by using efficient parameterized procedural layout generators. Fast performance estimation is achieved by using pre-compiled SPMs, stored as efficient DDD-like structures called Element Coefficient Diagrams. Techniques have been developed to include layout geometry effects in the SPMs. The accuracy and efficiency of the parasitic inclusion technique as well as the proposed methodology have been demonstrated by comparisons to traditional synthesis methods. The proposed methodology is used for the synthesis of opamps and filters and is demonstrated to achieve effective performance closure.
The generation of approximate linear symbolic expressions for analog integrated circuits requires the use of an appropriate error-control strategy. The error-control strategy determines both correctness and compactness of the approximate expression. This paper presents an evaluation of different errorcontrol strategies that fit within the flat symbolic analysis, using simplification during generation techniques for large analog integrated circuits. The theoretical exposition is illustrated with experimental results that allow a comparison of the proposed methods.
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