False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Liou, Jing-Jia; Krstić, A.; Wang, Li-C.; Cheng, Kwang-Ting

doi:10.1145/513918.514061

Cited by 95 publications

(53 citation statements)

References 17 publications

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“…There are two approaches to static timing analysis: path-based [9][10][11][12][13][14] and block- -20]. The path-based approach can be regarded as a depth-first search, and it employs a given a set of critical paths.…”

Section: A Timing Analysismentioning

confidence: 99%

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

Kim

Walker

2006

Seventh International Workshop on Microprocessor Test and Verification (MTV'06)

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Chair of Advisory Committee: Dr. Duncan Moore Henry Walker As semiconductor technology is scaled and voltage level is reduced, the impact of the variation in power supply has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of power supply noise is inevitable because high correlations exist between supply voltage and delay. Supply noise analysis has often used a vector-based timing analysis approach. Finding a set of test vectors in vector-based approaches, however, is very expensive, particularly during the design phase, and becomes intractable for larger circuits in DSM technology.In this work, two novel vectorless approaches are described such that increases in circuit delay, because of power supply noise, can be efficiently, quickly estimated.Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less than 2%, and both of my approaches are 67 times faster than the traditional vector-based approach. Also, the results show the importance of considering care-bits, which sensitize the longest paths during the power supply noise analysis.

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Section: A Timing Analysismentioning

confidence: 99%

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

Kim

Walker

2006

Seventh International Workshop on Microprocessor Test and Verification (MTV'06)

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“…Furthermore, these variations are increasing with each new generation of technology. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under such types of uncertainty, and has been the subject of intense research recently [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The result of SSTA is the prediction of parametric yield at a given target performance for a design.…”

Section: Introductionmentioning

confidence: 99%

An accurate sparse-matrix based framework for statistical static timing analysis

et al. 2012

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Statistical Static Timing Analysis has received wide attention recently and emerged as a viable technique for manufacturability analysis. To be useful, however, it is important that the error introduced in SSTA be significantly smaller than the manufacturing variations being modeled. Achieving such accuracy requires careful attention to the delay models and to the algorithms applied. In this paper, we propose a new sparse-matrix based framework for accurate path-based SSTA, motivated by the observation that the number of timing paths in practice is sub-quadratic based on a study of industrial circuits and the ISCAS89 benchmarks. Our sparse-matrix based formulation has the following advantages: (a) It places no restrictions on process parameter distributions; (b) It embeds accurate polynomial-based delay model which takes into account slope propagation naturally; (c) It takes advantage of the matrix sparsity and high performance linear algebra for efficient implementation. Our experimental results are very promising.

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“…With the shrinking feature size in VLSI technology, the impact of process variation is increasingly felt. To address the effect, great amount of research has been done recently, such as the clock skew analysis under process variation [4][5][6][7][8][9][10], statistical performance analysis [9,10], worst case performance analysis [11,12], parametric yield estimation [12,13], impact analysis on micro architecture [12,13] and delay fault [14,15] test under process variation [14][15][16][17]. As the technology reaches deep submicron or nanometer regime, the errors due to process variations becomes prominent [17][18][19].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Propagation Delay Deviation under Process Induced Threshold Voltage Variation

Verma¹,

Kaushik²,

Singh³

2011

IJCA

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Process variation has become a major concern in the design of many nanometer circuits, including interconnect pipelines. The primary sources of manufacturing variation include Deposition, Chemical Mechanical Planarization (CMP), Etching, Resolution Enhancement Technology (RET). Process variations manifest themselves as the uncertainties of circuit performance, such as delay, noise and power consumption. The performance of VLSI/ULSI chip is becoming less predictable as device dimensions shrinks below the sub-100-nm scale. The reduced predictability can be attributed to poor control of the physical features of devices and interconnects during the manufacturing process. Variations in these quantities maps to variations in the electrical behavior of circuits. Threshold voltage of a MOSFET varies due to changes in oxide thickness; substrate, polysilicon and implant impurity level; and surface charge. This paper provides a comprehensive analysis of the effect of threshold variation on the propagation delay through driver-interconnect-load (DIL) system. The impact of process induced threshold variations on circuit delay is discussed for three different technologies i.e 130nm, 70nm and 45nm. The comparison of results between these three technologies shows that as device size shrinks, the process variation issues becomes dominant during design cycle and subsequently increases the uncertainty of the delays.

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False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation

Cited by 95 publications

References 17 publications

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits

An accurate sparse-matrix based framework for statistical static timing analysis

Analysis of Propagation Delay Deviation under Process Induced Threshold Voltage Variation

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