Unlike stuck-at fault testing, delay testing is closely tied to the test application strategy. This means that before tests for delay faults are derived it is necessary to know how these tests will be applied to the circuit. The testing strategy depends on the type of the circuit (combinational, scan, non-scan or partial scan sequential) as well as on the speed of the testing equipment. Ordinarily, testing delay defects requires that the test vectors be applied to the circuit at its intended operating speed. However, since high speed testers require huge investments, testers currently used in test facilities could be slower than the new designs that need to be tested on them. Testing high speed designs on slower testers requires special test application and test generation strategies.The focus of this chapter is on different test application schemes for combinational and sequential circuits. Techniques used for testing scan as well as non-scan designs are described. Also, the issue of testing high speed designs using slow testers is addressed and some of the currently available solutions to this problem are described.
We propose a new statistical timing analysis algorithm, which produces arrival-time random variables for all internal signals and primary outputs for cell-based designs with all cell delays modeled as random variables. Our algorithm propagates probabilistic timing events through the circuit and obtains final probabilistic events (distributions) at all nodes. The new algorithm is deterministic and flexible in controlling run time and accuracy. However, the algorithm has exponential time complexity for circuits with reconvergent fanouts. In order to solve this problem, we further propose a fast approximate algorithm. Experiments show that this approximate algorithm speeds up the statistical timing analysis by at least an order of magnitude and produces results with small errors when compared with Monte Carlo methods.
We propose a new methodology based on incremental logic restructuring for post-layout performance improvement. The new post-layout logic restructuring technique allows to use accurate interconnection delays for performance optimization, while the incremental nature of the technique guarantees convergence between logic synthesis and layout. The technique can be further integrated with other post-layout optimization techniques such as gate sizing and buffer insertion. Experimental results show that this technique combined with post-layout buffer insertion can achieve an additional 15% improvement in performance compared to designs produced by timing-driven logic optimization followed by pre-layout buffer insertion followed by timing-driven physical design.
IntroductionPerformance-driven logic synthesis followed by performance-driven layout [1] has become a necessity for designing high performance circuits. However, this loosely coupled two-phase timing optimization methodology has serious limitations for deep-submicron-based designs in which interconnection delays become the dominant factor in determining the circuit speed. Accurate information regarding the interconnection delays is not available during the logic synthesis phase and the interconnection delays are just roughly estimated in this phase. Therefore, errors in the estimation could result in a logic design far-off from an optimal one.Recently, an ATPG-based approach, named Redundancy Addition and Removal, was proposed for combinational and synchronous sequential logic optimization [3][4] [5]. This approach optimizes the networks through iterative addition and removal of redundant connections. The redundancy addition and removal technique can identify alternative connections or gates for any given connection. For performance optimization, we can remove a connection on a critical path and replace it by one of its alternative connections/gates not on the critical path. Since
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